33.5.2 CMCC Configuration Register
This register can only be written if WPCFG is cleared in CMCC Write Protection Register .
| Name: | CMCC_CFG |
| Offset: | 0x04 |
| Reset: | 0x0000000020 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| LOCK | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PRGCSIZE[2:0] | DCDIS | ICDIS | GCLKDIS | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 1 | 0 | 0 | 0 | 0 | |||
Bit 8 – LOCK Configuration Lock Until Next System Reset (Write-once)
| Value | Description |
|---|---|
| 0 | No effect |
| 1 | CMCC_CFG cannot be written until a system reset occurs. |
Bits 6:4 – PRGCSIZE[2:0] Programmable Cache Size
| Value | Name | Description |
|---|---|---|
| 0 | - |
Reserved |
| 1 | PRGCSIZE_2KB |
Programmable cache size is 2 Kbytes |
| 2 | PRGCSIZE_4KB |
Programmable cache size is 4 Kbytes (default value) |
| 3 | PRGCSIZE_8KB |
Programmable cache size is 8 Kbytes |
| 4 | PRGCSIZE_16KB |
Programmable cache size is 16 Kbytes |
Bit 2 – DCDIS Data Caching Disable
Note: DCDIS is only relevant for unified cache and data cache architecture.
| Value | Description |
|---|---|
| 0 |
Data caching enabled. |
| 1 | Data caching disabled. |
Bit 1 – ICDIS Instruction Caching Disable
Note: ICDIS is only relevant for unified cache and Instruction cache architecture
| Value | Description |
|---|---|
| 0 |
Instruction caching enabled. |
| 1 | Instruction caching disabled. |
Bit 0 – GCLKDIS Disable Clock Gating
| Value | Description |
|---|---|
| 0 |
Clock gating is activated. |
| 1 |
Clock gating is disabled. |