33.5.7 CMCC Monitor Configuration Register
| Name: | CMCC_MCFG |
| Offset: | 0x28 |
| Reset: | 0x00000000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| MODE[1:0] | |||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 | |||||||
Bits 1:0 – MODE[1:0] Cache Controller Monitor Counter Mode
| Value | Name | Description |
|---|---|---|
| 0 | CYCLE_COUNT | Cycle counter |
| 1 | IHIT_COUNT | Instruction hit counter, Only relevant for unified cache and instruction cache architecture. |
| 2 | DHIT_COUNT | Data hit counter, Only relevant for unified cache and data cache architecture. |