33.5.3 CMCC Control Register
This register can only be written if WPCR is cleared in CMCC Write Protection Mode Register.
| Name: | CMCC_CTRL |
| Offset: | 0x08 |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| LOCK | |||||||||
| Access | W | ||||||||
| Reset | – |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CEN | |||||||||
| Access | W | ||||||||
| Reset | – |
Bit 8 – LOCK Control Lock Until Next System Reset (Write-once)
| Value | Description |
|---|---|
| 0 | No effect |
| 1 | CMCC_CTRL cannot be written until a system reset occurs. |
Bit 0 – CEN Cache Controller Enable
| Value | Description |
|---|---|
| 0 | The cache controller is disabled. |
| 1 | The cache controller is enabled. |