21.7.22 PIO Privilege Interrupt Enable Register
This register can only be written if the WPITEN bit is cleared in the PIO Privilege Write Protection Mode Register.
| Name: | PIO_P_IERx |
| Offset: | 0x1020 + x*0x40 [x=0..2] |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| P31 | P30 | P29 | P28 | P27 | P26 | P25 | P24 | ||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| P23 | P22 | P21 | P20 | P19 | P18 | P17 | P16 | ||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| P15 | P14 | P13 | P12 | P11 | P10 | P9 | P8 | ||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| P7 | P6 | P5 | P4 | P3 | P2 | P1 | P0 | ||
| Access | W | W | W | W | W | W | W | W | |
| Reset | – | – | – | – | – | – | – | – |
Bits 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 – Px Input Change Interrupt Enable
| Value | Description |
|---|---|
| 0 | No effect. |
| 1 | Enables the Input Change interrupt on the I/O line of the I/O group x. |