29.9.8 TUxyCLK

Clock Input Selector

Note:

This register is not available when the module is chained and operated as a Secondary module.

Name:

TUxyCLK


Bit	7	6	5	4	3	2	1	0
				CLK[4:0]
Access				R/W	R/W	R/W	R/W	R/W
Reset				0	0	0	0	0

Bits 4:0 – CLK[4:0] Clock Input Selector

Table 29-5. TUxyCLK Clock Input Selections
CLK	Clock Input
`11111 - 11011`	Reserved
`11010`	CLC8_OUT
`11001`	CLC7_OUT
`11000`	CLC6_OUT
`10111`	CLC5_OUT
`10110`	CLC4_OUT
`10101`	CLC3_OUT
`10100`	CLC2_OUT
`10011`	CLC1_OUT
`10010`	NCO1_OUT
`10001`	PWM3S1P2_OUT
`10000`	PWM3S1P1_OUT
`01111`	PWM2S1P2_OUT
`01110`	PWM2S1P1_OUT
`01101`	PWM1S1P2_OUT
`01100`	PWM1S1P1_OUT
`01011`	CCP2_OUT
`01010`	CCP1_OUT
`01001`	CLKREF_OUT
`01000`	EXTOSC
`00111`	SOSC
`00110`	MFINTOSC (31.25 kHz)
`00101`	MFINTOSC (500 kHz)
`00100`	LFINTOSC
`00011`	HFINTOSC
`00010`	F_OSC
`00001`	TUIN1PPS
`00000`	TUIN0PPS

Reset States:

POR/BOR = 00000

All Other Resets = uuuuu

This register is not available when the module is chained and operated as a Secondary module.

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