29.9.2 TUxyCON1

Timer Control Register 1
Note:
  1. Clock synchronization delays apply.
  2. This bit is held at zero if a Start has occurred (the counter is “running”), but ERS is holding the counter at the value zero when RESET = ‘b01 (level-triggered).
  3. The clearing of the ON bit in One Shot mode is subject to clock synchronization delays. Refer to the Synchronous vs. Asynchronous Operation and One Shot Mode sections for details.
  4. This bit is not clock synchronized and only needs to be changed while ON = 0.
  5. This bit is subject to clock synchronization delays. See Timer Counter and Capture Registers for details.
  6. If the counter is disabled (ON = 0) or if the module is frozen during debugging, then the timer clock has been disabled; the effect of setting CLR or CAPT command bits depends on the clock synchronization setting. If CSYNC = 0, the corresponding action is performed immediately. If CSYNC = 1, the corresponding action is delayed until the clock resumes (even in Frozen state while debugging). See also Timer Counter and Capture Registers.
  7. A capture event can also be triggered by other means. See Timer Counter and Capture Registers for details.
  8. If the CAPT command is near-coincident with a Stop event, the captured value may represent the first event that occurs.
  9. The captured value is read by setting RDSEL = 0 and reading TUxyCR.
  10. This bit may be set by software to invoke an interrupt or DMA operation.
  11. The interrupt flags will be set even if the corresponding interrupt is disabled.
  12. The PRIF interrupt will not occur if the user writes the PR value to the TUxyTMR counter register directly.
  13. The CIF interrupt trigger requires a running timer.
  14. This register is not available when the module is chained and operated as a Secondary module.
Name: TUxyCON1

Bit 76543210 
 RUNOSENCLRLIMITCAPTPRIFZIFCIF 
Access RR/WR/S/HCR/WR/S/HCR/W/HSR/W/HSR/W/HS 
Reset 00000000 

Bit 7 – RUN  Timer Run/Stop Status (Read-Only)(1,2)

Reset States: 
POR/BOR = 0
All Other Resets = u
ValueDescription
1 Timer is running (counting) and not being held in Reset by ERS (per EPOL bit selection)
0 Timer is not counting or is held in Reset by ERS

Bit 6 – OSEN  One Shot Mode Enable(3,4)

Reset States: 
POR/BOR = 0
All Other Resets = u
ValueDescription
1 The counter operates in One Shot mode; ON will be cleared by a Stop condition
0 The counter can be repeatedly started by the ERS signal

Bit 5 – CLR  Timer Counter “Clear” Command(5,6)

Writing this bit with ‘0’ has no effect.
Reset States: 
POR/BOR = 0
All Other Resets = u
ValueDescription
1 Once set, the timer counter and the internal prescaler counter are cleared, then this bit is cleared (the captured value of TUxyCR is unchanged)
0 Clearing action is complete (or not started)

Bit 4 – LIMIT  Limit Mode Enable(4)

This bit is relevant when RESET = ‘b00 (Continuous mode) and counter equals PR.
Reset States: 
POR/BOR = 0
All Other Resets = u
ValueDescription
1 Counter value remains equal to PR (unchanged); no additional interrupts occur
0 Counter value goes tor PR+1 when clocked

Bit 3 – CAPT  Timer “Capture” Command(5,6,7,8,9)

Writing this bit with ‘0’ has no effect.
Reset States: 
POR/BOR = 0
All Other Resets = u
ValueDescription
1 Once set, the counter value is captured in TUxyCR and this bit is cleared
0 TUxyCR update is complete (or not started)

Bit 2 – PRIF  Period Match Interrupt Flag(10,11,12)

Reset States: 
POR/BOR = 0
All Other Resets = u
ValueDescription
1 The counter has incremented from PR-1 to PR
0 The counter has not incremented from PR-1 to PR since this bit was last cleared

Bit 1 – ZIF  Zero Interrupt Flag(10,11)

Reset States: 
POR/BOR = 0
All Other Resets = u
ValueDescription
1 The counter has reset or rolled over to zero
0 The counter has not reset or rolled over since this bit was last cleared

Bit 0 – CIF  Capture Interrupt Flag(10,11,13)

Reset States: 
POR/BOR = 0
All Other Resets = u
ValueDescription
1 A capture event has occurred
0 A capture event has not occurred since this bit was last cleared
Clock synchronization delays apply. This bit is held at zero if a Start has occurred (the counter is “running”), but ERS is holding the counter at the value zero when RESET = ‘b01 (level-triggered). The clearing of the ON bit in One Shot mode is subject to clock synchronization delays. Refer to the Synchronous vs. Asynchronous Operation and One Shot Mode sections for details. This bit is not clock synchronized and only needs to be changed while ON = 0. This bit is subject to clock synchronization delays. See Timer Counter and Capture Registers for details. If the counter is disabled (ON = 0) or if the module is frozen during debugging, then the timer clock has been disabled; the effect of setting CLR or CAPT command bits depends on the clock synchronization setting. If CSYNC = 0, the corresponding action is performed immediately. If CSYNC = 1, the corresponding action is delayed until the clock resumes (even in Frozen state while debugging). See also Timer Counter and Capture Registers. A capture event can also be triggered by other means. See Timer Counter and Capture Registers for details. If the CAPT command is near-coincident with a Stop event, the captured value may represent the first event that occurs. The captured value is read by setting RDSEL = 0 and reading TUxyCR. This bit may be set by software to invoke an interrupt or DMA operation. The interrupt flags will be set even if the corresponding interrupt is disabled. The PRIF interrupt will not occur if the user writes the PR value to the TUxyTMR counter register directly. The CIF interrupt trigger requires a running timer. This register is not available when the module is chained and operated as a Secondary module.