6 Appendix 3: Multi-Lane 1G IOD CDR Design

In a multi-lane design, Ethernet traffic from multiple RJ45 cables comes into FPGA through PHY. In such cases, multiple RX and TX ports must be assigned from the PolarFire GPIO Banks to form multiple SGMII links with the PHY. The following figure shows the placement of I/O Banks and PLLs in a PolarFire device (MPF300).

Figure 6-1. I/O Banks and PLL Placement in MPF300

Each Bank has multiple I/O lanes and each I/O lane includes six I/O pairs. The lane controller available in each I/O lane has a clock recovery unit, which is used for the clock recovery of that lane. Therefore, only one SGMII link can be realized from an I/O lane.

For an 8-lane design, eight I/O lanes are used to form eight SGMII links. To enable sharing of the PF_IOD_CDR_CCC, the selection of these I/O lanes must be made in any of the following ways:

  • Lanes of the same bank can be selected vertically up to half of the side
  • Lanes of the same bank can be selected horizontally up to half of the side
  • Lanes from vertical and horizontal banks can be selected
Note: In Libero SoC, when I/O lanes are selected from Bank 5 or 2, or from both and placed, PF_IOD_CDR_CCC selects the SW PLL and is placed in SW. If all I/O lanes are selected from Bank 4, PF_IOD_CDR_CCC selects the NW PLL and is placed in NW.

When the reference clock for all the links is the same:

  • PF_IOD_CDR_CCC can be shared across all IOD blocks (PF_IOD_CDR) for the HSIO BANK clocks and transmit clock (TX_CLK)
  • PF_IOD_CDR_CCC uses an internal lane controller to generate the DLL delay code and share it with all IOD blocks. The DLL delay code is required for phase tuning/adjustment

To conclude, the following IOD resources are used to create an 8-lane design in a PolarFire MPF300 device:

  • One PF_IOD_CDR_CCC with a lane controller for DLL delay update
  • Eight I/O lanes and lane controllers for clock recovery

The following figure shows the high-level block diagram of an 8-lane design implemented using Libero SoC PolarFire.

Figure 6-2. 8 Lane 1G IOD CDR Design in PolarFire®

As per the preceding figure, eight PF_IOD_CDR instances are instantiated from GPIO Banks 5 and 2 to form eight links. The Clock Conditioning Circuit (CCC), available in the South-West corner, is configured in the PLL-DLL cascaded mode for the clock recovery and DLL delay update.

Apart from eight lane controllers for clock recovery, an additional lane controller from PF_IOD_CDR_CCC is inferred during synthesis for sharing the DLL delay update. This optimizes the utilization of lane controllers in the device.