Introduction

PolarFire® FPGAs support 1G (1000BASE-T) Ethernet solutions for various networking applications. In PolarFire devices, 10/100/1000 Mbps (1G) Ethernet is implemented using the CoreTSE Media Access Control (MAC) soft IP core. The CoreTSE IP implements a Serial Gigabit Media-Independent Interface (SGMII) with an Ethernet PHY. This Ethernet interface can be implemented in the FPGA by using either a transceiver or a GPIO with Clock and Data Recovery (CDR) capability. Both these features are provided by the PF_XCVR and the PF_IOD_CDR IP cores.

GPIOs in PolarFire devices operate at speeds of up to 1.066 Gbps for single-ended standards and 1.25 Gbps for differential standards. Each I/O has an I/O digital (IOD) logic block that supports gearing up of the output data rate and gearing down of the input data rate. The IOD block with CDR circuitry (PF_IOD_CDR IP) deserializes high-speed Ethernet input data and transfers it to the FPGA fabric at lower speeds. It also serializes the lower-speed Ethernet data from the FPGA fabric and transfers to the high-speed Ethernet PHY.

Note: The protocol standard uses “Master” and “Slave.” The equivalent Microchip terminology used in this document is Initiator and Target, respectively.