8 Appendix 5: References
(Ask a Question)This section lists the documents that provide more information about the IP cores used in the 1G loopback demo design and about PolarFire 1G Ethernet Solutions in general.
- For more information about PF_IOD_CDR_CCC and PF_IOD_CDR, see PolarFire FPGA and PolarFire SoC FPGA User I/O User Guide
- For more information about CoreTSE, see HB0549: CoreTSE Handbook from the Libero SoC Catalog
- For more information about PF_CCC, see PolarFire FPGA and PolarFire SoC FPGA Clocking Resources User Guide
- For more information about PF_SRAM_AXI_AHBL, see PolarFire FPGA and PolarFire SoC FPGA Fabric User Guide
- For more information about CoreAHBLite, see CoreAHBLite Handbook from the Libero SoC Catalog
- For information about COREAHBTOAPB3, see COREAHBTOAPB3 Handbook from the Libero SoC Catalog
- For more information about CoreAPB3, see CoreAPB3 Handbook from the Libero SoC Catalog
- For more information about CoreUARTapb, see CoreUARTapb Handbook from the Libero SoC Catalog
- For more information about CoreSPI, see HB0089: CoreSPI Handbook from the Libero SoC Catalog
- For more information about PF_INIT_MONITOR, see PolarFire FPGA and PolarFire SoC FPGA Power-Up and Resets User Guide
- For more information about MIV_RV32, see MIV_RV32 Handbook from the Libero SoC Catalog
- For general information about PolarFire 1G Ethernet Solutions, see UG0687: PolarFire FPGA 1G Ethernet Solutions User Guide
- For more information about the PolarFire Evaluation board, see UG0747: PolarFire FPGA Evaluation Kit User Guide