1 Design Description
(Ask a Question)This document describes how to run the 1G Ethernet loopback demo design, which is a reference design created to demonstrate 1G Ethernet loopback using GPIO on a PolarFire Evaluation Board. The demo design is built using the PF_IOD_CDR_CCC, the PF_IOD_CDR, the CoreTSE, and the Mi-V soft processor IP cores. The reference design is for a single SGMII lane (single RJ45 cable). For information about how to build a multi-lane (multiple links) design, see Appendix 3: Multi-Lane 1G IOD CDR Design.
You can program the demo design using either of the following options:
- Using the pre-generated
.jobfile: To program the device using the.jobfile provided along with the demo design files, see Appendix 1: Programming the Device Using FlashPro Express. - Using Libero SoC: To program the device using Libero SoC, see Libero Design Flow.
A license is required to use the CoreTSE IP core. To request a license, contact FPGA_marketing@microchip.com.