18.8.2 Sleep Configuration
| Name: | SLEEPCFG |
| Offset: | 0x01 |
| Reset: | 0x02 |
| Property: | PAC Write-Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SLEEPMODE[2:0] | |||||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 | ||||||
Bits 2:0 – SLEEPMODE[2:0] Sleep Mode
Note: A small latency happens between the
store instruction and actual writing of the SLEEPCFG register due to bridges.
Software has to make sure the SLEEPCFG register reads the wanted value before
executing WFI instruction.
| Value | Name | Definition |
|---|---|---|
| 0x0 | Reserved | - |
| 0x1 | Reserved | - |
| 0x2 | IDLE | CPU, AHBx, and APBx clocks are OFF |
| 0x3 | Reserved | Reserved |
| 0x4 | STANDBY | All Clocks are OFF |
| 0x5 | HIBERNATE | Backup domain is ON as well as some PDRAMs |
| 0x6 | BACKUP | Only Backup domain is powered ON |
| 0x7 | OFF | All power domains are powered OFF |