18.8.3 Interrupt Enable Clear

This register allows the user to disable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Set (INTENSET) register.
Name: INTENCLR
Offset: 0x04
Reset: 0x00
Property: PAC Write-Protection

Bit 76543210 
        SLEEPRDY 
Access W 
Reset 0 

Bit 0 – SLEEPRDY Sleep Mode Entry Ready Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will clear the Sleep Mode Entry Ready Interrupt Enable bit and the corresponding interrupt request.

ValueDescription
0 The Sleep Mode Entry Ready interrupt is disabled.
1 The Sleep Mode Entry Ready interrupt is enabled and will generate an interrupt request when the Sleep Mode Entry Ready Interrupt Flag is set.