18.8.4 Interrupt Enable Set

This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Interrupt Enable Clear (INTENCLR) register.

Name:	INTENSET
Offset:	0x05
Reset:	0x00
Property:	PAC Write-Protection


Bit	7	6	5	4	3	2	1	0
								SLEEPRDY
Access								R/W
Reset								0

Bit 0 – SLEEPRDY Sleep Mode Entry Ready Interrupt Enable

Writing a '0' to this bit has no effect.

Writing a '1' to this bit will set the Sleep Mode Entry Ready Interrupt Enable bit and enable the Sleep Mode Entry Ready interrupt.

Value	Description
0	The Sleep Mode Entry Ready interrupt is disabled.
1	The Sleep Mode Entry Ready interrupt is enabled.