15.8.6 AHB Mask

Note: All "Reserved" bits should be set to 1.

Name:	AHBMASK
Offset:	0x10
Reset:	0x00FFFFFF
Property:	PAC Write-Protection


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16
	NVMCTRL_CACHE	NVMCTRL_SMEEPROM	QSPI_2X	PUKCC	ICM	CAN1	CAN0	SDHC1
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	1	1	1	1	1	1	1	1


Bit	15	14	13	12	11	10	9	8
	SDHC0	GMAC	QSPI	PAC	Reserved	USB	DMAC	CMCC
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	1	1	1	1	1	1	1	1


Bit	7	6	5	4	3	2	1	0
	Reserved	NVMCTRL	Reserved	DSU	HPB3	HPB2	HPB1	HPB0
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	1	1	1	1	1	1	1	1

Bit 23 – NVMCTRL_CACHE NVMCTRL_CACHE AHB Clock Enable

Value	Description
0	The AHB clock for the NVMCTRL_CACHE is stopped.
1	The AHB clock for the NVMCTRL_CACHE is enabled.

Bit 22 – NVMCTRL_SMEEPROM NVMCTRL_SMEEPROM AHB Clock Enable

Value	Description
0	The AHB clock for the NVMCTRL_SMEEPROM is stopped.
1	The AHB clock for the NVMCTRL_SMEEPROM is enabled.

Bit 21 – QSPI_2X QSPI_2X AHB Clock Enable

Value	Description
0	The AHB clock for the QSPI_2X is stopped.
1	The AHB clock for the QSPI_2X is enabled.

Bit 20 – PUKCC PUKCC AHB Clock Enable

Value	Description
0	The AHB clock for the PUKCC is stopped.
1	The AHB clock for the PUKCC is enabled.

Bit 19 – ICM ICM AHB Clock Enable

Value	Description
0	The AHB clock for the ICM is stopped.
1	The AHB clock for the ICM is enabled.

Bits 17, 18 – CANn CANn AHB Clock Enable

Value	Description
0	The AHB clock for the CANn is stopped.
1	The AHB clock for the CANn is enabled.

Bits 15, 16 – SDHCn SDHCn AHB Clock Enable

Value	Description
0	The AHB clock for the SDHCn is stopped.
1	The AHB clock for the SDHCn is enabled.

Bit 14 – GMAC GMAC AHB Clock Enable

Value	Description
0	The AHB clock for the GMAC is stopped.
1	The AHB clock for the GMAC is enabled.

Bit 13 – QSPI QSPI AHB Clock Enable

Value	Description
0	The AHB clock for the QSPI is stopped.
1	The AHB clock for the QSPI is enabled.

Bit 12 – PAC PAC AHB Clock Enable

Value	Description
0	The AHB clock for the PAC is stopped.
1	The AHB clock for the PAC is enabled.

Bits 11,7,5 – Reserved Reserved bits

Reserved bits are unused and reserved for future use. For compatibility with future devices, always write reserved bits to their reset value. If no reset value is given, write 0.

Bit 10 – USB USB AHB Clock Enable

Value	Description
0	The AHB clock for the USB is stopped.
1	The AHB clock for the USB is enabled.

Bit 9 – DMAC DMAC AHB Clock Enable

Value	Description
0	The AHB clock for the DMAC is stopped.
1	The AHB clock for the DMAC is enabled.

Bit 8 – CMCC CMCC AHB Clock Enable

Value	Description
0	The AHB clock for the CMCC is stopped.
1	The AHB clock for the CMCC is enabled.

Bit 6 – NVMCTRL NVMCTRL AHB Clock Enable

Value	Description
0	The AHB clock for the NVMCTRL is stopped.
1	The AHB clock for the NVMCTRL is enabled.

Bit 4 – DSU DSU AHB Clock Enable

Value	Description
0	The AHB clock for the DSU is stopped.
1	The AHB clock for the DSU is enabled.

Bit 3 – HPB3 AHB-APB Bridge D AHB Clock Enable AHB Clock Enable

Value	Description
0	The AHB clock for the APBD is stopped.
1	The AHB clock for the APBD is enabled.

Bit 2 – HPB2 AHB-APB Bridge C AHB Clock Enable AHB Clock Enable

Value	Description
0	The AHB clock for the APBC is stopped.
1	The AHB clock for the APBC is enabled.

Bit 1 – HPB1 AHB-APB Bridge B AHB Clock Enable AHB Clock Enable

Value	Description
0	The AHB clock for the APBB is stopped.
1	The AHB clock for the APBB is enabled.

Bit 0 – HPB0 AHB-APB Bridge A AHB Clock Enable AHB Clock Enable

Value	Description
0	The AHB clock for the APBA is stopped.
1	The AHB clock for the APBA is enabled.

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