40.8.33 Preset Value Register

One of the Preset Value Registers is effective based on the selected bus speed mode. The table below defines the conditions to select one of the PVRs.

Table 40-3. Preset Value Register Select Condition
Selected Bus Speed Mode	VS18EN (HC2R)	HSEN (HC1R)	UHSMS (HC2R)
Default Speed	0	0	don’t care
High Speed	0	Response Timeout Error	don’t care
Reserved	1	don’t care	Other values

The following table shows the effective Preset Value Register according to the Selected Bus Speed mode.

Table 40-4. Preset Value Registers
PVRx	Selected Bus Speed Mode	Signal Voltage
PVR0	Initialization	3.3V or 1.8V
PVR1	Default Speed	3.3V
PVR2	High Speed	3.3V

When Preset Value Enable (PVALEN) in HC2R is set to 1, SDCLK Frequency Select (SDLCKFSEL) and Clock Generator Select (CLKGSEL) in CCR are automatically set based on the Selected Bus Speed mode. This means that the user does not need to set these fields when preset is enabled. A Preset Value Register for Initialization (PVR0) is not selected by Bus Speed mode. Before starting the initialization sequence, the user needs to set a clock preset value to SDCLKFSEL in CCR. PVALEN can be set to 1 after the initialization is completed.

Note: Preset Values in PVRx registers are not supposed to be written by the user. However, the user can modify preset values only if Capabilities Write Enable (CAPWREN) is written to 1 in CACR.

Name:	PVR
Offset:	0x60 + n*0x02 [n=0..7]
Reset:	0x0000
Property:	Read/Write


Bit	15	14	13	12	11	10	9	8
	DRVSEL[1:0]					CLKGSEL	SDCLKFSEL[9:8]
Access	R/W	R/W				R/W	R/W	R/W
Reset	0	0				0	0	0


Bit	7	6	5	4	3	2	1	0
	SDCLKFSEL[7:0]
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0	0	0

Bits 15:14 – DRVSEL[1:0] Driver Strength Select Value for Initialization

Refer to DRVSEL in HC2R.

Bit 10 – CLKGSEL Clock Generator Select Value for Initialization

Refer to CGGSEL in CCR.

Bits 9:0 – SDCLKFSEL[9:0] SDCLK Frequency Select Value for Initialization

Refer to SDCLKFSEL in CCR.