40.8.27 Capabilities 1 Register

Note: The Capabilities 1 Register is not supposed to be written by the user.
Name: CA1R
Offset: 0x44
Reset: 0x00000070
Property: -

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
 CLKMULT[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 15141312111098 
   TSDR50 TCNTRT[3:0] 
Access R/WR/WR/WR/WR/W 
Reset 00000 
Bit 76543210 
  DRVDSUPDRVCSUPDRVASUP DDR50SUPSDR104SUPSDR50SUP 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 

Bits 23:16 – CLKMULT[7:0] Clock Multiplier

This field indicates the multiplier factor between the Base Clock (BASECLK) used for the Divided Clock Mode and the Multiplied Clock (MULTCLK) used for the Programmable Clock mode (refer to CCR).

Reading this field to 0 means that the Programmable Clock mode is not supported.

F MULTCLK = F BASECLK × CLKMULT + 1

Bit 13 – TSDR50 Use Tuning for SDR50

If this bit is set to 1, the peripheral requires tuning to operate SDR50 (tuning is always required to operate SDR104).

ValueDescription
0

SDR50 does not require tuning.

1

SDR50 requires tuning.

Bits 11:8 – TCNTRT[3:0] Timer Count For Re-Tuning

This field indicates an initial value of the Re-Tuning Timer for Re-Tuning Mode (RTMODE) 1 to 3. Reading this field at 0 means that the Re-Tuning Timer is disabled. The Re-Tuning Timer initial value ranges from 0 to 1024 seconds.

T TIMER = 2 TCNTRT + 1 Seconds

Bit 6 – DRVDSUP Driver Type D Support

ValueDescription
0

Driver type D is not supported.

Bit 5 – DRVCSUP Driver Type C Support

ValueDescription
0

Driver type C is not supported.

Bit 4 – DRVASUP Driver Type A Support

ValueDescription
0

Driver type A is not supported.

Bit 2 – DDR50SUP DDR50 Support

ValueDescription
0

DDR50 mode is not supported.

Bit 1 – SDR104SUP SDR104 Support

ValueDescription
0

SDR104 mode is not supported.

1

SDR104 mode is supported.

Bit 0 – SDR50SUP SDR50 Support

ValueDescription
0

SDR50 mode is not supported.

1

SDR50 mode is supported.