40.8.26 Capabilities 0 Register

This field indicates usage of a slot by a specific system. An peripheral control register set is defined per slot.

Embedded Slot for One Device means that only one non-removable device is connected to a bus slot.

The Standard Host Driver controls a removable card (SLTYPE = 0) or one embedded device (SLTYPE = 1) connected to an SD bus slot.

Refer to section “Asynchronous Interrupt” in the “SDIO Simplified Specification V3.00”.

This bit indicates if the peripheral supports the 64-bit Address Descriptor mode and is connected to the 64-bit address system bus.

This bit indicates whether the peripheral supports the Suspend/Resume functionality. If this bit is set to 0, the user does not issue either Suspend or Resume commands because the Suspend and Resume mechanism (refer to “Suspend and Resume Mechanism” in the “SD Host Controller Simplified Specification V3.00” ) is not supported.

This bit indicates whether the peripheral is capable of using SDMA to transfer data between system memory and the peripheral directly.

This bit indicates whether the peripheral and the system support High Speed mode and they can supply SDCLK frequency from 25MHz to 50MHz.

This bit indicates whether the peripheral is capable of using ADMA2.

This bit indicates whether the peripheral is capable of using the 8-bit Bus Width mode.

This value indicates the frequency of the base clock (BASECLK). The user uses this value to calculate the clock divider value (refer to SDCLK Frequency Select (SDCLKFSEL) in CCR).

If this field is set to 0, the user must get the information via another method.

This bit shows the unit of the base clock frequency used to detect Data Timeout Error.

This bit shows the timeout clock frequency (TEOCLK) used to detect Data Timeout Error.

If this field is set to 0, the user must get the information via another method.

The Timeout Clock Unit (TEOCLKU) defines the unit of this field’s value.

– TEOCLKU = 0:

– TEOCLKU = 1: