40.8.17 Normal Interrupt Status Register

If any of the bits in EISTR are set, then this bit is set. Therefore, the user can efficiently test for an error by checking this bit first. This bit is read-only.

This bit is set to 1 when the peripheral received a Boot Acknowledge pattern from the e.MMC.

This bit can only be set to 1 if NISTER.BOOTAR is set to 1. An interrupt can only be generated if NISIER.BOOTAR is set to 1.

Writing this bit to 1 clears this bit.

Writing this bit to 1 does not clear this bit. It is cleared by resetting the SD card interrupt factor. In 1-bit mode, the peripheral detects the Card Interrupt without SDCLK to support wake-up. In 4-bit mode, the Card Interrupt signal is sampled during the interrupt cycle, so there are some sample delays between the interrupt signal from the SD card and the interrupt to the system.

When this bit has been set to 1 and the user needs to start this interrupt service, Card Interrupt Status Enable (CINT) in NISTER may be set to 0 in order to clear the card interrupt statuses latched in the peripheral and to stop driving the interrupt signal to the system. After completion of the card interrupt service (it should reset interrupt factors in the SD card and the interrupt signal may not be asserted), set NISTER.CINT to 1 and start sampling the interrupt signal again.

Interrupt detected by DAT[1] is supported when there is one card per slot. In case of a shared bus, interrupt pins are used to detect interrupts. If 0 is set to Interrupt Pin Select (INTPSEL) in SBCR, this status is effective. If a non-zero value is set to INTPSEL, INT_A, INT_B or INT_C is used as device interrupts.

This bit can only be set to 1 if NISTER.CREM is set to 1. An interrupt can only be generated if NISIER.CREM is set to 1.

This status is set to 1 if Card Inserted (CARDINS) in PSR changes from 1 to 0. When the user writes this bit to 1 to clear this status, the status of PSR.CARDINS must be confirmed because the card detect state may possibly be changed when the user clears this bit and no interrupt event can be generated.

This bit can only be set to 1 if NISTER.CREM is set to 1. An interrupt can only be generated if NISIER.CREM is set to 1.

Writing this bit to 1 clears this bit.

This status is set if Card Inserted (CARDINS) in PSR changes from 0 to 1. When the user writes this bit to 1 to clear this status, the status of PSR.CARDINS must be confirmed because the card detect state may possibly be changed when the user clears this bit and no interrupt event can be generated.

This bit can only be set to 1 if NISTER.CINS is set to 1. An interrupt can only be generated if NISIER.CINS is set to 1.

Writing this bit to 1 clears this bit.

This status is set to 1 if the Buffer Read Enable (BUFRDEN) changes from 0 to 1. Refer to BUFRDEN in PSR.

This bit can only be set to 1 if NISTER.BRDRDY is set to 1. An interrupt can only be generated if NISIER.BRDRDY is set to 1.

Writing this bit to 1 clears this bit.

This status is set to 1 if the Buffer Write Enable (BUFWREN) changes from 0 to 1. Refer to BUFWREN in PSR.

This bit can only be set to 1 if NISTER.BWRRDY is set to 1. An interrupt can only be generated if NISIER.BWRRDY is set to 1.

Writing this bit to 1 clears this bit.

This status is set if the peripheral detects the Host SDMA Buffer boundary during transfer. Refer to SDMA Buffer Boundary (BOUNDARY) in BSR.

In case of ADMA, by setting the “int” field in the descriptor table, the peripheral rises this status flag when the descriptor line is completed. This status flag does not rise after Transfer Complete (TRFC).

This bit can only be set to 1 if NISTER.DMAINT is set to 1. An interrupt can only be generated if NISIER.DMAINT is set to 1.

Writing this bit to 1 clears this bit.

If the Stop At Block Gap Request (STPBGR) in BGCR is set to 1, this bit is set when either a read or a write transaction is stopped at a block gap. If STPBGR is not set to 1, this bit is not set to 1.

In the case of a Read transaction:

This bit is set at the falling edge of the DAT Line Active (DLACT) status (when the transaction is stopped at SD bus timing). The Read Wait must be supported in order to use this function. Refer to section “Read Transaction Wait / Continue Timing” in the “SD Host Controller Simplified Specification V3.00” about the detailed timing.

In the case of a Write transaction:

This bit is set at the falling edge of the Write Transfer Active (WTACT) status (after getting the CRC status at SD bus timing). Refer to section “Write Transaction Wait / Continue Timing” in the “SD Host Controller Simplified Specification V3.00” for more details on the sequence of events.

This bit can only be set to 1 if NISTER.BLKGE is set to 1. An interrupt can only be generated if NISIER.BLKGE is set to 1.

Writing this bit to 1 clears this bit.

This bit is set when a read/write transfer and a command with Busy is completed.

In the case of a Read Transaction:

This bit is set at the falling edge of the Read Transfer Active Status. The interrupt is generated in two cases. The first is when a data transfer is completed as specified by the data length (after the last data has been read to the system). The second is when data has stopped at the block gap and completed the data transfer by setting the Stop At Block Gap Request (STPBGR) in BGCR (after valid data has been read to the system). Refer to section “Read Transaction Wait / Continue Timing” in the “SD Host Controller Simplified Specification V3.00” for more details on the sequence of events.

In the case of a Write Transaction:

This bit is set at the falling edge of the DAT Line Active (DLACT) status. This interrupt is generated in two cases. The first is when the last data is written to the card as specified by the data length and the Busy signal is released. The second is when data transfers are stopped at the block gap by setting Stop At Block Gap Request (STPBGR) in BGCR and data transfers are completed. (After valid data is written to the card and the Busy signal is released). Refer to section “Write Transaction Wait / Continue Timing” in the “SD Host Controller Simplified Specification V3.00” for more details on the sequence of events.

In the case of command with Busy:

This bit is set when Busy is de-asserted. Refer to DAT Line Active (DLACT) and Command Inhibit (DAT) (CMDINHD) in PSR.

This bit can only be set to 1 if NISTER.TRFC is set to 1. An interrupt can only be generated if NISIER.TRFC is set to 1.

Writing this bit to 1 clears this bit.

The table below shows that Transfer Complete (TRFC) has a higher priority than Data Timeout Error (DATTEO). If both bits are set to 1, execution of a command can be considered to be completed.

This bit is set when getting the end bit of the command response. Auto CMD12 and Auto CMD23 consist of two responses. Command Complete is not generated by the response of CMD12 or CMD23, but it is generated by the response of a read/write command. Refer to Command Inhibit (CMD) in PSR for details on how to control this bit.

This bit can only be set to 1 if NISTER.CMDC is set to 1. An interrupt can only be generated if NISIER.CMDC is set to 1.

Writing this bit to 1 clears this bit.

The table below shows that Command Timeout Error (CMDTEO) has a higher priority than Command Complete (CMDC). If both bits are set to 1, it can be considered that the response was not received correctly.