31.7.8 Channel n Control
This register allows the user to configure channel n. To write to this register, do a single, 32-bit write of all the configuration data.
| Name: | CHANNELn |
| Offset: | 0x20 + n*0x08 [n=0..31] |
| Reset: | 0x00008000 for CHANNEL0-11, and 0x00000000 for CHANNEL12-31 |
| Property: | PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ONDEMAND | RUNSTDBY | EDGSEL[1:0] | PATH[1:0] | ||||||
| Access | RW | RW | RW | RW | RW | RW | |||
| Reset | 1 | 0 | 0 | 0 | 0 | 0 | |||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EVGEN[6:0] | |||||||||
| Access | RW | RW | RW | RW | RW | RW | RW | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bit 15 – ONDEMAND Generic Clock On Demand
This bit is used to determine whether the generic clock is requested.
This bit has no effect for channels when asynchronous path is selected or for channels with asynchronous support only.
This bit is always read zero for channels with asynchronous support only.
| Value | Description |
|---|---|
| 0 | Generic clock for a channel is always on, if the channel is configured and generic clock source is enabled. |
| 1 | Generic clock is requested on demand while an event is handled |
Bit 14 – RUNSTDBY Run in Standby
This bit is used to define the behavior during standby sleep mode, for a resynchronized channel.
This bit has no effect for channels when asynchronous path is selected or for channels with asynchronous support only.
This bit is always read zero for channels with asynchronous support only.
| Value | Description |
|---|---|
| 0 | The channel is disabled in standby sleep mode. |
| 1 | The channel is not stopped in standby sleep mode and depends on the CHANNEL.ONDEMAND bit. |
Bits 11:10 – EDGSEL[1:0] Edge Detection Selection
These bits set the type of edge detection to be used on the channel.
These bits must be written to zero when using the asynchronous path.
| Value | Name | Description |
|---|---|---|
| 0x0 | NO_EVT_OUTPUT | No event output when using the resynchronized or synchronous path |
| 0x1 | RISING_EDGE | Event detection only on the rising edge of the signal from the event generator |
| 0x2 | FALLING_EDGE | Event detection only on the falling edge of the signal from the event generator |
| 0x3 | BOTH_EDGES | Event detection on rising and falling edges of the signal from the event generator |
Bits 9:8 – PATH[1:0] Path Selection
These bits are used to choose which path will be used by the selected channel.
| Value | Name | Description |
|---|---|---|
| 0x0 | SYNCHRONOUS | Synchronous path |
| 0x1 | RESYNCHRONIZED | Resynchronized path |
| 0x2 | ASYNCHRONOUS | Asynchronous path |
| Other | - | Reserved |
Bits 6:0 – EVGEN[6:0] Event Generator Selection
These bits are used to choose the event generator to connect to the selected channel.
| Value | Name | Description |
|---|---|---|
| 0x00 | NONE | No event generator selected |
| 0x01 - 0x02 | OSCCTRL_XOSC_FAILx | XOSC fail detection x=0..1 |
| 0x03 | OSC32KCTRL_XOSC32K_FAIL | XOSC32K fail detection |
| 0x04 - 0x0B | RTC_PERx | RTC period x=0..7 |
| 0x0C - 0x0F | RTC_CMP | RTC comparison x=0..3 |
| 0x10 | RTC_TAMPER | RTC tamper detection |
| 0x11 | RTC_OVF | RTC overflow |
| 0x12 - 0x21 | EIC_EXTINT | EIC external interrupt x=0..15 |
| 0x22 - 0x25 | DMAC_CH | DMA channel x=0..3 |
| 0x26 | PAC_ACCERR | PAC Acc. error |
| 0x27 | Reserved | - |
| 0x28 | Reserved | - |
| 0x29 | TCC0_OVF | TCC0 Overflow |
| 0x2A | TCC0_TRG | TCC0 Trigger Event |
| 0x2B | TCC0_CNT | TCC0 Counter |
| 0x2C - 0x31 | TCC0_MCx | TCC0 Match/Compare x=0..5 |
| 0x32 | TCC1_OVF | TCC1 Overflow |
| 0x33 | TCC1_TRG | TCC1 Trigger Event |
| 0x34 | TCC1_CNT | TCC1 Counter |
| 0x35 - 0x38 | TCC1_MCx | TCC1 Match/Compare x=0..3 |
| 0x39 | TCC2_OVF | TCC2 Overflow |
| 0x3A | TCC2_TRG | TCC2 Trigger Event |
| 0x3B | TCC2_CNT | TCC2 Counter |
| 0x3C - 0x3E | TCC2_MCx | TCC2 Match/Compare x=0..2 |
| 0x3F | TCC3_OVF | TCC3 Overflow |
| 0x40 | TCC3_TRG | TCC3 Trigger Event |
| 0x41 | TCC3_CNT | TCC3 Counter |
| 0x42 - 0x43 | TCC3_MCx | TCC3 Match/Compare x=0..1 |
| 0x44 | TCC4_OVF | TCC4 Overflow |
| 0x45 | TCC4_TRG | TCC4 Trigger Event |
| 0x46 | TCC4_CNT | TCC4 Counter |
| 0x47 - 0x48 | TCC4_MCx | TCC4 Match/Compare x=0..1 |
| 0x49 | TC0_OVF | TC0 Overflow |
| 0x4A - 0x4B | TC0_MCx | TC0 Match/Compare x=0..1 |
| 0x4C | TC1_OVF | TC1 Overflow |
| 0x4D - 0x4E | TC1_MCx | TC1 Match/Compare x=0..1 |
| 0x4F | TC2_OVF | TC2 Overflow |
| 0x50 - 0x51 | TC2_MCx | TC2 Match/Compare x=0..1 |
| 0x52 | TC3_OVF | TC3 Overflow |
| 0x53 - 0x54 | TC3_MCx | TC3 Match/Compare x=0..1 |
| 0x55 | TC4_OVF | TC4 Overflow |
| 0x56 - 0x57 | TC4_MCx | TC4 Match/Compare x=0..1 |
| 0x58 | TC5_OVF | TC5 Overflow |
| 0x59 - 0x5A | TC5_MCx | TC5 Match/Compare x=0..1 |
| 0x5B | TC6_OVF | TC6 Overflow |
| 0x5C - 0x5D | TC6_MCx | TC6 Match/Compare x=0..1 |
| 0x5E | TC7_OVF | TC7 Overflow |
| 0x5F - 0x60 | TC7_MCx | TC7 Match/Compare x=0..1 |
| 0x61 | PDEC_OVF | PDEC Overflow |
| 0x62 | PDEC_ERR | PDEC Error |
| 0x63 | PDEC_DIR | PDEC Direction |
| 0x64 | PDEC_VLC | PDEC VLC |
| 0x65 - 0x66 | PDEC_MCx | PDEC MCx x=0..1 |
| 0x67 | ADC0_RESRDY | ADC0 RESRDY |
| 0x68 | ADC0_WINMON | ADC0 Window Monitor |
| 0x69 | ADC1_RESRDY | ADC1 RESRDY |
| 0x6A | ADC1_WINMON | ADC1 Window Monitor |
| 0x6B - 0x6C | AC_COMPx | AC Comparator, x=0..1 |
| 0x6D | AC_WIN | AC0 Window |
| 0x6E - 0x6F | DAC_EMPTYx | DAC empty, x=0..1 |
| 0x70 - 0x71 | DAC_RESRDYx | DAC RSRDY, x=0..1 |
| 0x72 | GMAC_TSU_CMP | GMAC Timestamp CMP |
| 0x73 | TRNG_READY | TRNG ready |
| 0x74 - 0x77 | CCL_LUTOUT | CCL LUTOUT |
| 0x78-0x7F | Reserved | Reserved |