51.6.1.1 Initialization

The I2S features two Clock Units, one Transmit Serializer, and One Receive Serializer. The Transmit Serializer uses Clock Unit 0, while the Receive Serializer can either share the same Clock Unit 0 or use the Clock Unit 1.

Before enabling the I2S, the following registers must be configured:

  • Clock Control registers (CLKCTRLn)
  • Serializer Control registers (TXCTRL and/or RXCTRL)

In Host mode, one of the generic clocks for the I2S must also be configured to operate at the required frequency, as described in Principle of Operation.

  • fs is the sampling frequency that defines the frame period
  • CLKCTRLn.NBSLOTS defines the number of slots in each frame
  • CLKCTRLn.SLOTSIZE defines the number of bits in each slot
  • SCKn frequency must be fSCKn = fs × number_of_slots × number_of_bits_per_slot)

Once the configuration has been written, the I2S Clock Units and Serializers can be enabled by writing a '1' to the CKENn, TXEN, and/or RXEN bits and to the ENABLE bit in the Control register (CTRLA). The Clock Unit n can be enabled alone, in Controller Mode, to output clocks to the MCKn, SCKn, and FSn pins. The Clock Units must be enabled if Serializers are enabled.

The Clock Units, the Transmit Serializer and the Receive Serializer can be disabled independently by writing a '0' to CTRLA.CKENn, CTRLA.TXEN, and CTRLA.RXEN, respectively. Once requested to stop, they will only stop when the pending transmit frames will be completed, if any. When requested to stop, the ongoing reception of the current slot will be completed and then the Serializer will be stopped.

Example Requirements: fs=48kHz, MCKn=384×fs

If a 384×fs MCKn Host Clock is required (i.e. 18.432 MHz), the I2S generic clock could run at 18.432 MHz with a Host Clock Output Division Factor of 1 (selected by writing CLKCTRLn.MCKOUTDIV=0x0) in order to obtain the desired MCKn frequency.

When using 6 slots per frame (CLKCTRLn.NBSLOTS=0x5) and 32-bit slots (CLKCTRLn.SLOTSIZE=0x3), the desired SCKn frequency is

fSCKn = 48 kHz × 6 × 32 = 9.216 MHz

This frequency can be achieved by dividing the I2S generic clock output of 18.432 MHz by factor 2: Writing CLKCTRLn.MCKDIV=0x1 will select the correct division factor and output the desired SCKn frequency of 9.216 MHz to the SCKn pin.

If MCKn is not required, the generic clock could be set to 9.216 MHz and CLKCTRLn.MCKDIV=0x0.