15.8.9 APBC Mask

Name:	APBCMASK
Offset:	0x1C
Reset:	0x00002000
Property:	PAC Write-Protection


Bit	31	30	29	28	27	26	25	24

Access
Reset


Bit	23	22	21	20	19	18	17	16

Access
Reset


Bit	15	14	13	12	11	10	9	8
		CCL	QSPI		ICM	TRNG	AES	AC
Access		R/W	R/W		R/W	R/W	R/W	R/W
Reset		0	1		0	0	0	0


Bit	7	6	5	4	3	2	1	0
	PDEC	TC5	TC4	TCC3	TCC2	GMAC
Access	R/W	R/W	R/W	R/W	R/W	R/W
Reset	0	0	0	0	0	0

Bit 14 – CCL CCL APBC Mask Clock Enable

Value	Description
0	The APBC clock for the CCL is stopped.
1	The APBC clock for the CCL is enabled.

Bit 13 – QSPI QSPI APBC Mask Clock Enable

Value	Description
0	The APBC clock for the QSPI is stopped.
1	The APBC clock for the QSPI is enabled.

Bit 11 – ICM ICM APBC Mask Clock Enable

Value	Description
0	The APBC clock for the ICM is stopped.
1	The APBC clock for the ICM is enabled.

Bit 10 – TRNG TRNG APBC Mask Clock Enable

Value	Description
0	The APBC clock for the TRNG is stopped.
1	The APBC clock for the TRNG is enabled.

Bit 9 – AES AES APBC Mask Clock Enable

Value	Description
0	The APBC clock for the AES is stopped.
1	The APBC clock for the AES is enabled.

Bit 8 – AC AC APBC Mask Clock Enable

Value	Description
0	The APBC clock for the AC is stopped.
1	The APBC clock for the AC is enabled.

Bit 7 – PDEC PDEC APBC Mask Clock Enable

Value	Description
0	The APBC clock for the PDEC is stopped.
1	The APBC clock for the PDEC is enabled.

Bits 5, 6 – TCn TCn APBC Mask Clock Enable

Value	Description
0	The APBC clock for the TCn is stopped.
1	The APBC clock for the TCn is enabled.

Bits 3, 4 – TCCn TCCn APBC Mask Clock Enable

Value	Description
0	The APBC clock for the TCCn is stopped.
1	The APBC clock for the TCCn is enabled.

Bit 2 – GMAC GMAC APBC Mask Clock Enable

Value	Description
0	The APBC clock for the GMAC is stopped.
1	The APBC clock for the GMAC is enabled.

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