28.8.4 CLCnSEL0

Generic CLCn Data 1 Select Register
Name: CLCnSEL0
Offset: 0x058E

Bit 76543210 
   D1S[5:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset xxxxxx 

Bits 5:0 – D1S[5:0] CLCn Data1 Input Selection

Table 28-2. CLC Input Selection
DyS Input SourceDyS (cont.)Input Source (cont.)
[0] 0000 0000CLCIN0PPS[21] 0001 0101PWM3_OUT
[1] 0000 0001CLCIN1PPS[22] 0001 0110PWM4_OUT
[2] 0000 0010CLCIN2PPS[23] 0001 0111PWM5_OUT
[3] 0000 0011CLCIN3PPS[24] 0001 1000NCO1_OUT
[4] 0000 0100FOSC[25] 0001 1001C1_OUT
[5] 0000 0101HFINTOSC[26] 0001 1010ZCD_OUT
[6] 0000 0110LFINTOSC[27] 0001 1011IOC
[7] 0000 0111MFINTOSC (500 kHz)[28] 0001 1100CLC1_OUT
[8] 0000 1000MFINTOSC (32 kHz)[29] 0001 1101CLC2_OUT
[9] 0000 1001SFINTOSC (1 MHz)[30] 0001 1110CLC3_OUT
[10] 0000 1010SOSC[31] 0001 1111CLC4_OUT
[11] 0000 1011EXTOSC[32] 0010 0000TX1/CK1
[12] 0000 1100ADCRC[33] 0010 0001TX2/CK2
[13] 0000 1101TMR0_overflow[34] 0010 0010SDA1/SDO1
[14] 0000 1110TMR1_overflow[35] 0010 0011SCL1/SCK1
[15] 0000 1111TMR2_Postscaled_OUT[36] 0010 0100SDA2/SDO2
[16] 0001 0000TMR3_overflow[37] 0010 0101SCL2/SCK2
[17] 0001 0001TMR4_Postscaled_OUT[38] 0010 0110CWG1A_OUT
[18] 0001 0010TMR6_Postscaled_OUT[39] 0010 0111CWG1B_OUT
[19] 0001 0011CCP1_OUT[40] 0010 1000 - [63] 0011 1111Reserved
[20] 0001 0100CCP2_OUT
Reset States: 
POR/BOR = xxxxxx
All Other Resets = uuuuuu