41.4.7 Analog-to-Digital Converter (ADC) Conversion Timing Specifications

Table 41-13. 
Standard Operating Conditions (unless otherwise stated)
Param. No.Sym.CharacteristicMin.Typ. †Max.UnitsConditions
AD20TADADC Clock Period———μsUsing FOSC as the ADC clock source ADOCS = 0
—2—μsUsing ADCRC as the ADC clock source ADOCS = 1
AD21TCNVConversion Time—14 TAD+2TCY——Using FOSC as the ADC clock source ADOCS = 0
—16 TAD+2TCY——Using ADCRC as the ADC clock source ADOCS = 1
AD22THCDSample-and-Hold Capacitor Disconnect Time—2 TAD+1TCY——Using FOSC as the ADC clock source ADOCS = 0
—3 TAD+2TCY——Using ADCRC as the ADC clock source ADOCS = 1

* These parameters are characterized but not tested.

† Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

Figure 41-10. ADC Conversion Timing (ADC Clock FOSC-Based)
Figure 41-11. ADC Conversion Timing (ADC Clock from ADCRC)
Note:
  1. If the ADC clock source is selected as ADCRC, a time of TCY is added before the ADC clock starts. This allows the SLEEP instruction to be executed.