29.2.4.1 I2C Host Mode Operation
The host device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released.
0
’. Serial data is transmitted eight bits at a time.
After each byte is transmitted, an Acknowledge bit is received. Start and Stop conditions
are output to indicate the beginning and the end of a serial transfer.In Host Receive mode, the first byte transmitted contains the client
address of the transmitting device (seven bits) and the R/W bit. In this case, the R/W bit will be logic ‘1
’. Thus, the first byte transmitted is a 7-bit client address followed by a
‘1
’ to indicate the receive bit. Serial data is
received via SDA, while SCL outputs the serial clock. Serial data is received eight bits at
a time. After each byte is received, an Acknowledge sequence is transmitted. Start and Stop
conditions indicate the beginning and end of transmission.
A Baud Rate Generator is used to set the clock frequency output on SCL. See Baud Rate Generator for more details.