29.2.3.7.3 7-Bit Transmission with Address Hold Enabled
Setting the AHEN bit enables additional clock stretching and interrupt generation after the eighth falling edge of a received matching address. Once a matching address has been clocked in, CKP is cleared and the SSPxIF interrupt is set.
Figure 29-23 displays a standard waveform of a 7-bit address client transmission with AHEN enabled.
- Bus starts Idle.
- Host sends Start condition; the S bit is set; SSPxIF is set if SCIE is set.
- Host sends matching address with the R/W bit set. After the eighth falling edge of the SCL line the CKP bit is cleared and SSPxIF interrupt is generated.
- Client software clears SSPxIF.
- Client software reads the ACKTIM, R/W and D/A bits to determine the source of the interrupt.
- Client reads the address value from the SSPxBUF register, clearing the BF bit.
- Client software decides from this information if it wishes to ACK or NACK and sets the ACKDT bit accordingly.
- Client software sets the CKP bit, releasing SCL.
- Host clocks in the ACK value from the client.
- Client hardware automatically clears the CKP bit and sets SSPxIF after ACK if the R/W bit is set.
- Client software clears SSPxIF.
- Client loads value to transmit to the host into SSPxBUF, setting
the BF bit.Important: SSPxBUF cannot be loaded until after the ACK.
- Client software sets the CKP bit, releasing the clock.
- Host clocks out the data from the client and sends an ACK value on the ninth SCL pulse.
- Client hardware copies the ACK value into the ACKSTAT bit.
- Steps 10-15 are repeated for each byte transmitted to the host from the client.
- If the host sends a not ACK, the client releases the bus allowing the host to send a Stop and
end the communication.Important: Host must send a not ACK on the last byte to ensure that the client releases the SCL line to receive a Stop.