16.17.2.3 NFC Data Address
If five address cycles are used, the first address cycle is ADDR_CYCLE0. See HSMC_ADDR.
Name: | NFCDATA_ADDT |
Property: | Write-only |
Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
ADDR_CYCLE4[7:0] | |||||||||
Access | W | W | W | W | W | W | W | W | |
Reset |
Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
ADDR_CYCLE3[7:0] | |||||||||
Access | W | W | W | W | W | W | W | W | |
Reset |
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
ADDR_CYCLE2[7:0] | |||||||||
Access | W | W | W | W | W | W | W | W | |
Reset |
Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
ADDR_CYCLE1[7:0] | |||||||||
Access | W | W | W | W | W | W | W | W | |
Reset |
Bits 31:24 – ADDR_CYCLE4[7:0] NAND Flash Array Address Cycle 4
When five address cycles are used, ADDR_CYCLE4 is the fifth byte written to NAND Flash.
Bits 23:16 – ADDR_CYCLE3[7:0] NAND Flash Array Address Cycle 3
When five address cycles are used, ADDR_CYCLE3 is the fourth byte written to NAND Flash.
Bits 15:8 – ADDR_CYCLE2[7:0] NAND Flash Array Address Cycle 2
When five address cycles are used, ADDR_CYCLE2 is the third byte written to NAND Flash.
Bits 7:0 – ADDR_CYCLE1[7:0] NAND Flash Array Address Cycle 1
When five address cycles are used, ADDR_CYCLE1 is the second byte written to NAND Flash.