74.10.3.2 ULP2 Mode Operation

In ULP2 mode, all device power supplies are applied within their operating range, except VDDCPU. The power reduction is achieved by stopping the clock signals of the processor and/or its peripherals. The device is able to resume on wake-up events. Additional power savings are made by shutting down the VDDCPU power supply and thus eliminating any leakage power in the Cortex-A7 subsystem.

In this mode, the CPU cluster (Cortex-A7 + L1 and L2 cache memories) is powered down while all other registers and memories of the device are maintained(1). Upon wake-up triggered by an event (see detailed list), the VDDCPU power supply is re-applied and when the VDDCPU POR releases the CPU reset line, the device executes the ROM code @ 0x00000000.

Note:
  1. Some content is overwritten due to ROM code execution.

The following operations, based on procedures described in SDRAM Self-Refresh Mode, must be performed in this order. Code example is provided in software deliverables.

Entering ULP2 Mode

In ULP2 mode (unlike ULP0 mode) all clocks are off and the number of wake-up sources is limited to:
  • Any PIO line configured as a wake-up source in PMC_WCR
  • RTC alarm, RTT alarm
  • USB Resume from Suspend mode

To enter ULP2 mode:

  1. Enter SDRAM Self-refresh mode.
  2. Clear all pending events.
  3. Configure the wake-up source. RTT example:
    • Disable the interrupt for RTT.
    • Enable the RTT wake-up in the PMC Fast Start-Up Mode register (PMC_FSMR).
    • Set the RTT Alarm register (RTT_AR) to approximately 1 minute.
    • Perform an RTT Restart and enable the alarm interrupt.
  4. Suspend USB ports 0, 1 and 2.
  5. Disable all GCLK peripheral clocks.
  6. Disable PMC protection.
  7. Switch MCK0 to MAINCK.
  8. Set MDIV to 1 for MCK0.
  9. Switch the MCK source to MAINCK for all MCKs (1 to 4).
  10. Set MDIV to 1 for all MCKs (1 to 4).
  11. Turn off all eight PLLs.
  12. Turn on the Main RC.
  13. Switch MAINCK to Main RC.
  14. Turn off the Main Crystal Oscillator.
  15. Disable SYSC and SHDW write protections.
  16. Configure the expected event (RTT alarm, for example).
  17. Configure LPM in Automatic mode.
  18. Set Ultra Low-power 2 mode in PMC.
  19. Send a Wait for Event (WFE) command.

The system is now in ULP2 mode, waiting for the programmed event (such as RTT alarm).

Exiting ULP2 Mode

When the event occurs, the CPU power supply is recovered and the device executes the ROM code @ 0x00000000. The Reset Controller indicates "ULP Mode 2 reset" as reset type in the RSTC_SR.RSTTYP field. This flag is taken into account by the software to re-initialize the system and recover pre-ULP2 configuration.

A typical system re-initialization is as follows.

Regular ROM code initialization:

  1. Switch MCK0 to MAINCK.
  2. Set MDIV to 1 for MCK0.
  3. Start up CPUPLL (570 MHz).
  4. Switch MCK0 to CPUPLL with MDIV set to 4.
  5. Start up SYSPLL (378 MHz).
  6. Switch MCK1 to SYSPLL with MDIV set to 2.
  7. Switch MCK4 to SYSPLL with MDIV set to 1.
  8. Perform the required boot strategy.

User's configuration after exiting ULP2 (in user's code):

  1. Start up the Main Crystal Oscillator.
  2. Switch MAINCK to Main Crystal Oscillator.
  3. Modify clocks configuration (MCKx, GCLKx, etc.).
  4. Start up DDRPLL (533 MHz).
  5. Re-initialize SDRAM and exit Self-refresh mode.
  6. Recover data from SDRAM.