74.6.11 I2SMCC Timings

Timings are provided in the following domains:
  • 1.8V domain: VDDIO from 1.7V to 1.9V, maximum external capacitor = 15 pF, DRV= 1, SR = 1
  • 3.3V domain: VDDIO from 3.0V to 3.6V, maximum external capacitor = 15 pF, DRV= 0, SR = 1
Figure 74-36. I2SMCC Timing Diagram in Host Mode
Figure 74-37. I2SMCC Timing Diagram in Client Mode
Table 74-39. I2SMCC Timings
Symbol Parameter Min Max Unit
Host Mode
fI2SMCC_SCK Frequency in Host mode – 12.5 MHz
I2S0 I2SMCC_DINx setup time before I2SMCC_SCK rises 18 – ns
I2S1 I2SMCC_DINx hold time after I2SMCC_SCK rises 0 – ns
I2S2 I2SMCC_SCK falling to I2SMCC_DOUTx delay 0 7 ns
I2S3 I2SMCC_SCK falling to I2SMCC_WS delay 0 7 ns
Client Mode
fI2SMCC_SCK Frequency in Client mode – 12.5 MHz
I2S4 I2SMCC_DINx setup time before I2SMCC_SCK rises 3 – ns
I2S5 I2SMCC_DINx hold time after I2SMCC_SCK rises 1 – ns
I2S6 I2SMCC_WS setup time before I2SMCC_SCK rises 7 – ns
I2S7 I2SMCC_WS hold time after I2SMCC_SCK rises 0 – ns
I2S8 I2SMCC_SCK falling to I2SMCC_DOUTx delay 5 18 ns