50.5.5.1 Transmit Channel

Data are fed to the 32-word depth transmit FIFO of the DSP by writing into the ASRC_THRx that has been configured in the Channel Configuration register (ASRC_CH_CONF).

A data written in the ASRC_THRx register is automatically written into the corresponding transmit FIFO as long as the FIFO is ready to receive data (ASRC_ISRx.TXRDY=1).

When no more space is available in the transmit FIFO, the TXRDY flag falls and the TXFULL flag rises. Writing a data in the transmit FIFO when ASRC_ISRx.TXFULL =1 leads to an overflow and raises the ASRC_ISRx.TXOVR flag. The TXOVR flag is cleared on read.

The transmit FIFO is read at the sample rate defined in ASRC_TRIG.TRIGSELINx.

The DSP core reads the data transmit FIFO at the selected sampling frame rate. When the transmit FIFO is empty, the ASRC_ISRx.TXEMPTY flag rises. If a trigger event occurs while the FIFO is empty, an underrun is generated and the ASRC_ISRx.TXUDR flag rises. The TXUDR flag is cleared on read.

The transmit channel of the ASRC features a DMA channel chunk management. When the number of free spaces reaches the chunk size configured in the field ASRC_CH_CONF.CHUNKx, the ASRC_ISRx.TXCHUNK flag rises, ensuring that chunk size data can be written consecutively. This flag is cleared once the number of data written equals the value configured in ASRC_CH_CONF.CHUNKx.

For each DSP, the chunk size applies to receive and transmit channel management.

The DMA controller transfers must be configured with the same chunk size. Refer to the section “DMA Controller (XDMAC)”.