50.5.5.2 Receive Channel

Each data converted by a DSP is written into the corresponding 32-word depth receive FIFO and can be read in ASRC_RHRx that has been configured through ASRC_CH_CONF.

When at least one data is ready in the receive FIFO, the RXRDY flag rises and remains high as long as there is at least one data to be read in the FIFO.

When a receive FIFO has no more available space, the ASRC_ISRx.RXFULL flag rises. If the DSP writes a new data into the receive FIFO while RXFULL=1, the RXOVR flag rises and the data is not written into the receive FIFO. RXOVR flag is cleared on read.

Once all data contained in the receive FIFO have been read, the ASRC_ISRx.RXEMPTY flag rises. If a data is read while the receive FIFO is empty, an underrun occurs, the RXUDR flag rises. The RXUDR flag is cleared on read.

The receive FIFO features a DMA channel chunk management. When the number of written data reaches the chunk size configured in ASRC_CH_CONF.CHUNK, the ASRC_ISRx.RXCHUNK flag rises, ensuring that chunk size data can be read consecutively. This flag is cleared once the number of data read equals the value configured in ASRC_CH_CONF.CHUNKx.

For each DSP, the chunk size applies to receive and transmit channel management.

The DMA controller transfers must be configured with the same chunk size. Refer to the section “DMA Controller (XDMAC)”.