49.7.5 PDMC Interrupt Enable Register
This register can only be written if the WPITEN bit is cleared in PDMC_WPMR.
The following configuration values are valid for all listed bit names of this register:
0: No effect.
1: Enables the corresponding interrupt.
| Name: | PDMC_IER |
| Offset: | 0x14 |
| Reset: | – |
| Property: | Write-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | | | | WPERR | | | | | |
| Access | | | | W | | | | | |
| Reset | | | | – | | | | | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | | | | | | | | | |
| Access | | | | | | | | | |
| Reset | | | | | | | | | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | | | | | | | | | |
| Access | | | | | | | | | |
| Reset | | | | | | | | | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | RXOVR | RXUDR | RXCHUNK | RXFULL | RXEMPTY | RXRDY | |
| Access | | | W | W | W | W | W | W | |
| Reset | | | – | – | – | – | – | – | |
Bit 28 – WPERR Write Protect Event Interrupt
Enable
Bit 5 – RXOVR Receive Over Flow Interrupt Enable
Bit 4 – RXUDR Receive Under Flow Interrupt Enable
Bit 3 – RXCHUNK Receive FIFO Chunk Interrupt Enable
Bit 2 – RXFULL Receive FIFO Full Interrupt Enable
Bit 1 – RXEMPTY Receive FIFO Empty Interrupt Enable
Bit 0 – RXRDY Receive Ready Interrupt Enable
