49.7.2 PDMC Mode Register
This register can only be written if the WPEN bit is cleared in PDMC_WPMR.
| Name: | PDMC_MR |
| Offset: | 0x04 |
| Reset: | 0x10300000 |
| Property: | Read/Write |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| CHUNK[3:0] | SINC_OSR[3:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| SINCORDER[3:0] | OSR[1:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | |||
| Reset | 0 | 0 | 1 | 1 | 0 | 0 | |||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| PDMCEN3 | PDMCEN2 | PDMCEN1 | PDMCEN0 | ||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
Bits 31:28 – CHUNK[3:0] Chunk Size
Defines the DMA chunk size for RX channels.
Chunk size optimizes the number of trigger events sent to DMA for audio data transfer. Allowed values are 1, 2, 4, 8. Refer to section "DMA Controller (XDMAC)" for possible chunk sizes.
When the number of received data equals the value configured in PDMC_MR.CHUNK, the RXCHUNK flag rises.
Bits 27:24 – SINC_OSR[3:0] SINC Filter Oversampling Ratio
| Value | Name | Description |
|---|---|---|
| 0 | DISABLE | Audio Filtering mode. The SINC filter OSR is implicitly defined by the PDMC_MR.OSR field. |
| 1 | OSR8 | The SINC filter OSR is 8. |
| 2 | OSR16 | The SINC filter OSR is 16. |
| 3 | OSR32 | The SINC filter OSR is 32. |
| 4 | OSR64 | The SINC filter OSR is 64. |
| 5 | OSR128 | The SINC filter OSR is 128. |
| 6 | OSR256 | The SINC filter OSR is 256. |
Bits 23:20 – SINCORDER[3:0] SINC Filter Order
Defines the SINC filter order.
Values outside those defined in the following table are forbidden.
SINCORDER must be set to 3 when in Audio Filtering mode (SINC_OSR=0), as the audio filtering compensates the droop of the third order SINC filter.
| Value | Name | Description |
|---|---|---|
| 1 | ORDER1 | The SINC filter order is 1. |
| 2 | ORDER2 | The SINC filter order is 2. |
| 3 | ORDER3 | The SINC filter order is 3. Recommended if SINC_OSR=0. |
| 4 | ORDER4 | The SINC filter order is 4. |
| 5 | ORDER5 | The SINC filter order is 5. |
Bits 17:16 – OSR[1:0] Audio Oversampling Ratio
Oversampling ratio between the frequency of the clock sent to the PDMC and the output sampling rate when SINC_OSR=0. Audio filtering is performed in addition to SINC filtering.
| Value | Name | Description |
|---|---|---|
| 0 | – | Reserved |
| 1 | OSR64 | OSR is 64. |
| 2 | OSR128 | OSR is 128. |
| 3 | OSR256 | OSR is 256. |
Bits 0, 1, 2, 3 – PDMCENx PDMC Channel x Enable
| Value | Name | Description |
|---|---|---|
| 0 | DISABLE | PDMC is disabled. |
| 1 | ENABLE | PDMC is enabled. |