49.7.7 PDMC Interrupt Mask Register
The following configuration values are valid for all listed bit names of this register:
0: The corresponding interrupt is not enabled.
1: The corresponding interrupt is enabled.
| Name: | PDMC_IMR |
| Offset: | 0x1C |
| Reset: | 0x00000000 |
| Property: | Read-only |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| | | | | WPERR | | | | | |
| Access | | | | R | | | | | |
| Reset | | | | 0 | | | | | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| | | | | | | | | | |
| Access | | | | | | | | | |
| Reset | | | | | | | | | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| | | | | | | | | | |
| Access | | | | | | | | | |
| Reset | | | | | | | | | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| | | | RXOVR | RXUDR | RXCHUNK | RXFULL | RXEMPTY | RXRDY | |
| Access | | | R | R | R | R | R | R | |
| Reset | | | 0 | 0 | 0 | 0 | 0 | 0 | |
Bit 28 – WPERR Write Protection Event Interrupt
Mask
Bit 5 – RXOVR Receive Over Flow Interrupt Mask
Bit 4 – RXUDR Receive Under Flow Interrupt Mask
Bit 3 – RXCHUNK Receive FIFO Chunk Interrupt Mask
Bit 2 – RXFULL Receive FIFO Full Interrupt Mask
Bit 1 – RXEMPTY Receive FIFO Empty Interrupt Mask
Bit 0 – RXRDY Receive Ready Interrupt Mask
