38.5.7 Conversion Triggers

Conversions of the active analog channels are started with a software or hardware trigger. The software trigger is provided by writing the Control register (ADC_CR) with ADC_CR.START at 1.

The list of external/internal events is provided in ADC_MR. The hardware trigger is selected using ADC_MR.TRGSEL. The selected hardware trigger is enabled if TRGMOD = 1, 2 or 3 in the Trigger register (ADC_ TRGR).

The ADC also provides a dual trigger mode (ADC_TEMPMR.TEMPON=1) in which the highest index channel can be sampled at a rhythm different from the other channels. The trigger of the last channel is generated by the RTC. See Temperature Sensor.

ADC_TRGR.TRGMOD selects the hardware trigger from the following:

  • any edge, either rising or falling or both, detected on the external trigger pin ADTRG or internal triggers (provided by other peripherals)
  • a continuous trigger, meaning the ADC Controller restarts the next sequence as soon as it finishes the current one
  • a periodic trigger (generated by the ADC Controller), which is defined by programming ADC_TRGR.TRGPER

The minimum time between two consecutive trigger events must be strictly greater than the duration time of the longest conversion sequence according to configuration of registers ADC_MR, ADC_SEQRx (Channel Sequence register), ADC_CHSR (Channel Status register).

If a hardware trigger is selected, the start of a conversion is triggered after a delay starting at each rising edge of the selected signal. Due to asynchronous handling, the delay may vary in a range of two peripheral clock periods to one ADC clock period. This delay introduces sampling jitter in the A/D conversion process and may therefore degrade the conversion performance (e.g., SNR, THD).

Figure 38-6. Hardware Trigger Delay

Only one start command is necessary to initiate a conversion sequence on all the enabled channels. The ADC hardware logic automatically performs the conversions on the active channels, then waits for a new request. The Channel Enable (ADC_CHER) and Channel Disable (ADC_CHDR) registers enable the analog channels to be enabled or disabled independently.

If the ADC is used with a DMA channel, only the transfers of converted data from enabled channels are performed and the resulting data buffers should be interpreted accordingly.