38.5.15 Buffer Structure without FIFO

The DMA read channel is triggered when ADC_FMR.ENFIFO is set to 0 (see ENFIFO: Enable FIFO ) and each time a new data is stored in ADC_LCDR. The same structure of data is repeatedly stored in ADC_LCDR each time a trigger event occurs. Depending on the user mode of operation (ADC_MR, ADC_CHSR, ADC_SEQR1, ADC_SEQR2), the structure differs. Each data read to DMA buffer, carried on a half-word (16 bits), consists of last converted data right-aligned and when TAG is set in ADC_EMR, the four most significant bits carry the channel number, thus allowing an easier post-processing in the DMA buffer or a better checking of the DMA buffer integrity.

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