40 Revision History

Revision A (November 2023)

This is the initial version of the document.

Revision B (July 2024)

This revision incorporates the following updates:

  • Sections:
    • Updated Operating Conditions, High-Performance dsPIC33A DSP/CISC CPU, Controller Features, High-Resolution PWM, Two High-Speed Analog-to-Digital Converters, Other Analog Features, Peripheral Features, dsPIC33AK128MC106 Product Family, 1. Device Overview, 2.1 Basic Connection, 2.2 Decoupling Capacitors, 2.4 ICSP Pins, 3.1 Architectural Overview, 3.3.15.1.2 Interrupting a REPEAT Loop, 3.3.6 Exception Processing, 3.3.16 Data Space Address Generation Units (AGUs), 3.3.7.1 SR: CPU STATUS Register, 3.3.9 Alternate Working Register Arrays, 3.3.10.1 Software Stack Examples, 3.3.10.3 Stack Pointer Overflow, 3.3.12.1 Data Accumulators,3.3.12.2 Multiplier, 3.3.12.3 Data Accumulator Adder/Subtractor, 3.3.12.3.3 Data Space Write Saturation, 3.3.12.3.4 Accumulator Write Back, 3.3.12.5 Barrel Shifter, 3.3.12.7 DSP Engine Trap Events, 3.3.13 Divide Support, 3.3.17 MAC Instructions, 3.3.19 Address Register Dependencies, 3.3.12.2.1 DSP Multiply Instructions, 3.3.12.3 Data Accumulator Adder/Subtractor, 3.3.12.3.4 Accumulator Write Back, 3.3.15 Loop Constructs, 3.3.15.1 REPEAT Loop Construct, 3.3.15.1.1 REPEAT Operation, 3.3.16 Data Space Address Generation Units (AGUs), 3.4 Prefetch Buffer Unit (PBU), 3.4.3.2.1 Cache Invalidation when Writing to Flash, 4.1.1 Address Space, 4.2.3 Data Memory Organization, 4.2.4 Bus Matrix, 4.4.5 Bus Error, 5.4.6.2 Performing Fault Injection, 5.4.7.1 BIST at Start-up, 6. Flash Program Memory, 6.3.2.1.2 LOCK bit, User Page Erase Sequence, User Row Programming Sequence, 6.3.3 Flash ECCUser Word Programming Sequence, 7. Configuration Bits, 7.1 Configuration Register Summary, 8. Security Module, 8.3.2 User Configuration A (UCA), 8.3.2 User Configuration B (UCB), 9.3.2 Power-On Reset (POR), 9.3.6 Brown-Out Reset (BOR), 9.3.7 On-Chip Voltage Regulators, 10. Interrupt Controller, 10.3.1 Remappable Interrupt Table, 10.3.2 Collapsed Interrupt Vector, 10.7.1 CPU Priority, 10.9.1.1 Bus Error Traps, 11. I/O Ports with Edge Detect, 11.4.12.2.1 Clock Selection, 11.4.13 Boundary Scan Cell Connections, 11.7.3 I/O Integrity Module Operations in Sleep Mode, 12. Oscillator and Clocking Module, 12.1 Device-Specific Information, 12.2 Architectural Overview, 12.4.1 Clock Generators (CLKGEN), 12.4.1.1 Fail-Safe Clock Monitor (FSCM), 12.4.2 Phase-Locked Loop (PLL), 12.4.2.1 Input Clock Limitation at Start-up for PLL Mode, 12.4.2.2 PLL Lock Status, 12.4.2.3.1 Setup for Using PLL with the Primary Oscillator (POSC), 12.4.2.3.2 Setup for Using PLL with 8 MHz Internal FRC, 12.4.3 Primary Oscillator (POSC), 12.4.3.2 Primary Oscillator Pin Functionality,12.4.4 Internal Fast RC (FRC) Oscillator, 12.4.5 BFRC Oscillator, 15.4.6 Internal Low-Power RC (LPRC) Oscillator, 12.4.7 Clock Monitor, 12.4.7.1 Clock Monitor Overview, 12.4.7.2 Detection on Monitored Clock, Reference Clock Failure, 12.4.8 Reference Clock Output (REFOx), 13. Direct Memory Access (DMA) Controller, 13.4.12 Bit Manipulation, 14. PWM, 14.3.4.1.1 Master Clocking, 14.3.4.2.1 PWM Generator Clocking, 14.3.4.3.3 Shared Clocking, Frequency Scaling, 15. High-Speed, 12-Bit Low Latency ADC, 15.4.3.1 Sampling Time Requirements, 15.4.4 Conversions, 15.4.14.1.1 Error Compensation Coefficient Calculation, 16. High-Speed Analog Comparator with Slope Compensation DAC, 17. Quadrature Encoder Interface (QEI), 17.4.8 Interval Timer, 17.6 Interrupts, 18. Universal Asynchronous Receive Transmitter (UART), 18.4.1 Clocking and Baud Rate Configuration, 18.4.1.1 Legacy Mode, 18.4.1.2 Fractional Division Mode, 18.4.1.4 Auto-Baud Feature, 18.4.2.1 Asynchronous Mode, 18.4.2.1.1 Asynchronous Transmit, Setup for UART Transmit, Half-Duplex Transmit, 18.4.2.1.2 Asynchronous Receive, Setup for UART Receive, Receive Errors and Events, 18.4.2.1.6 Address Detect, Address Detect Receive, XON/XOFF, Wait Time, Post-ATR Initialization, 18.6.1 Interrupt Watermarks, 18.7.1 Sleep, 20. Inter-Integrated Circuit (I2C), 21.4.1 Transmit Mode, 21.4.1.2 CRC Calculation, 21.4.1.6 Asynchronous Transmitter Mode, 21.4.1.7 Synchronous Transmitter Mode, 21.4.2 Receive Mode, 21.4.2.4 Receive Setup Procedure, 21.4.2.6 Short PWM Code (SPC) Support, 21.7.1 Sleep Mode, 21.7.2 Idle Mode, 23.4.5 Timer Prescalers, 23.6.1 Timer Operation in Sleep Mode, 26.5.1 Generating Phase-Shifted Waveforms, 28.1 Device-Specific Information, 28.2 Architectural Overview, 28.4.1.1 Device Pin ESD Configuration, 28.4.4 ADC Input Considerations, 30. Watchdog Timer, 30.1 Device-Specific Information, 30.2 Architectural Overview, 32.3.1.3 Idle Mode, 32.3.1 Instruction-Based Power-Saving Modes, 32.3.1.2.1 Sleep Mode Entry, 32.3.1.2.3 Delay on Wake-up from Sleep, 34. In-Circuit Debugger and Product Identification System.
    • Added 4.1.2 Multiple Speed Peripheral Bus and Clock Overview, 12.2.1 Peripheral Clock Divider, 12.4.6 Internal Low-Power RC (LPRC) Oscillator, 13.4.1 Data Transfer Options, 13.4.7.1 Peripheral to Memory (Receive), 13.4.11 Ping-Pong, 13.4.12.1.1 Channel Chaining15. High-Speed, 12-Bit Low Latency ADC, 15.2 Architectural Overview, 15.4.3 Sampling and Conversion Timing, 15.4.6 Calibration. 15.4.14.1 Software Gain Error Compensation, 15.4.14.1.1 Error Compensation Coefficient Calculation, 15.4.14.1.2 Application of Error Compensation Coefficient, I2S Audio Host Mode of Operation, 15.2.2 Band Gap Reference, 16.4.4. Calibration and 38.1 Package Marking Information.
    • Removed One Instruction Word, One Instruction Cycle, One Instruction Word, Two Instruction Cycles, One Instruction Word, Two or Four Instruction Cycles (Program Flow Changes), Two Instruction Words, Four Instruction Cycles – GOTO or CALL, Address Register Dependencies. X Address Generation Unit, Y Address Generation Unit, Read After Write Dependency Rules, Instruction Stall Cycles, Instruction Stall Cycles and Interrupts, Instruction Stall Cycles and Flow Change Instructions, Instruction Stalls and REPEAT Loops, Data Space Arbiter Stalls, Coprocessor Interface, Coprocessor Instructions, Coprocessor Data Interface, Coprocessor Register Context, CPU Accessing Coprocessor Status,
  • Tables:
    • Updated Table 1. dsPIC33AK128MC106 Family, Table 2. 28-Pin SSOP Complete Pin Function Descriptions, Table 3. 28-Pin VQFN Complete Pin Function Descriptions, Table 4. 36-Pin VQFN Complete Pin Function Descriptions, Table 5. 48-Pin VQFN, TQFP Complete Pin Function Descriptions, Table 6. 64-Pin VQFN, TQFP Complete Pin Function Descriptions, Table 7. Pinout I/O Descriptions, Table 3-2. Programmer's Model Register Descriptions, Table 3-4. DSP Instructions that Use the Multiplier, Table 3-3. dsPIC33A Data Ranges, Table 4-1. Peripheral Bus Speed to Peripheral Mapping, Table 4-4. Target to Bus Error Index Mapping, 4.4.5.3 Target Bus Error Handling, Table 7-2. dsPIC33AK128MC106 Configuration Addresses, Table 10-1. Interrupt Vector Details, Table 11-9. PPS Availability by Package, Table 11-13. Output Selection for Remappable Pins (RPn), Table 11-10. Selectable Input Sources (Maps Input to Function), Table 12-1. Oscillator Summary, Table 12-2. Clock Generator Input and Destination, Table 12-3. Clock Generator Input Clock Selections, Table 12-4. PLL Input Clock Selections, Table 12-5. Clock Monitor CNTSEL/WINSEL Input Clock Selections, Table 12-7. Primary Oscillator Clock Source Options, Table 12-8 Clock Pin Function Selection, Table 13-1. DMA Summary Table, Table 13-2. DMA Channel Trigger Sources, Table 14-1. PWM Summary Table, Table 15-1. ADC Summary, Table 15-2. ADC External Input Availability, Table 15-3. TRG1SRC Trigger Source Selection Bits, Table 15-4. TRG2SRC Trigger Source Selection Bits, Table 15-5 FPDMDAC Calibration Register, Table 16-1. DAC Summary, Table 17-1. QEI Summary, Table 18-1. UART Summary, Table 18-2. Baud Clock Source Selection bits, Table 19-1. SPI Summary Table, Table 19-2. MCLKEN Host Clock Enable bit, Table 19-3. Device FIFO Depth, Table 20-1. I2C Summary Table, Table 21-1. SENT Summary Table, Table 22-1. BiSS Summary Table, Table 22-2. CLKSEL Macro Baud Clock Selection bit, Table 22-1. BiSS Summary TableTable 23-2. Timer1 Clock Source Select bit, Table 24-2. CLKSEL Time Base Clock Select bits, Table 26-1. PTG Summary Table,Table 28-1. CBG Summary Table, Table 29-1. Op Amp Summary Table, Table 29-2. Op Amp Availability by Device Package, Table 30-2. WDT Period Configurations, Table 31-1. DMT Summary, Table 32-1. Oscillator Delay, Table 35-1. Symbols Used in Opcode Descriptions, Table 35-2. Instruction Set Overview, Table 37-1. Absolute Maximum Ratings,Table 37-4. Thermal Packaging Characteristics,Table 37-5. Operating Voltage Specifications, Table 37-6. DC Characteristics: Operating Current (IDD), Table 37-7. Idle Current (IIDLE), Table 37-8. DC Characteristics: Power-Down Current (IPD), Table 37-9. DC Characteristics: Watchdog Timer Delta Current (ΔIWDT), Table 37-10. DC Characteristics: PWM Delta Current, Table 37-11. DC Characteristics: CLKGEN Delta Current, Table 37-12. DC Characteristics: PLL Delta Current, Table 37-13. DC Characteristics: ADC Δ Current, Table 37-14. DC Characteristics: Comparator + DAC Delta Current, Table 37-15. Op Amp Delta Current, Table 37-16. I/O Pin Input Specifications, Table 37-17. I/O Pin Input Leakage Specifications, Table 37-19. I/O Pin Output Specifications, Table 37-20. Program Memory Specifications, Table 37-21. Capacitive Loading Requirements on Output Pins, Table 37-22. External Clock Timing Requirements, Table 37-23. PLLn Timing Specifications, Table 37-24. Peripheral Input Clock Timing Specifications, Table 37-25. Internal FRC Accuracy, Table 37-26. I/O Timing Requirements, Table 37-27. Reset, Watchdog Timer Timing Requirements, Table 37-28. High-Speed PWMx Module Timing Requirements, Table 37-29. QEI Index Pulse Timing Requirements, Table 37-30. SPIx Maximum Data/Clock Rate Summary, Table 37-31. SPIx Host Mode (Half-Duplex, Transmit Only) Timing Requirements, Table 37-32. SPIx Host Mode (Full-Duplex, CKE = 1, CKP = X, SMP = 1), Table 37-33. SPIx Host Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 1) Timing Requirements, Table 37-34. SPIx Client Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 0) Timing Requirements, Table 37-35. SPIx Client Mode (Full-Duplex, CKE = 1, CKP = x, SMP = 0) Timing Requirements, Table 37-36. I2Cx Bus Data Timing Requirements (Host Mode), Table 37-38. UARTx Module I/O Timing Requirements, Table 37-39. ADC Module Specifications, Table 37-40. Die Temperature Diode Specifications, Table 37-41. High-Speed Analog Comparator Module Specifications, Table 37-42. DACx Module Specifications, Table 37-43. DACx Output (DACOUTx Pins) Specifications, Table 37-44. Current Bias Generator Specifications and Table 37-45. Operational Amplifier Specifications.
    • Added Table 7-3. dsPIC33AK128MC106 Backup Configuration Addresses, Table 7-4. Device ID and Revision Addresses, Table 7-5. Family Device Identifier, Table 8.3.5. Security Configuration Words, Table 14-2. MCLKSEL PWM Master Clock Selection, Table 15-4. TRG2SRC Trigger Source Selection Bits, Table 24-1. CCP Summary Table, Table 28-1. CBG Summary Table and Table 30-1. WDT Summary Table.
    • Removed Device Reset to Code Execution Start Time, CLKSEL DAC Clock Source Select bits, Doze Current (IDOZE) and Electrical Characteristics: BOR.
  • Registers:
    • Updated 3.2.9 Y AGU Modulo Addressing Start Address Register, 3.2.17 CPU STATUS Register, 4.3.4 BMX Error Status Register for Initiator, 4.3.5 BMX Error Status Register for Initiator, 4.3.6 BMX Error Status Register for Initiator, 4.3.7 BMX Error Status Register for CPU, 4.3.8 BMX Error Status Register for Initiator, 4.3.9 BMX Error Status Register for Initiator x, 5.3.3 BMX ECC RAM Fault Pointer Register, 6.2.1 Nonvolatile Memory (NVM) Control Register, 6.2.2 NVM Address Register, 6.2.3 NVM Write Data 0 Register, 6.2.4 NVM Write Data 1 Register, 6.2.5 NVM Write Data 2 Register, 6.2.6 NVM Write Data 3 Register, 6.2.7 NVM Source Data Address Register, 6.2.8 NVM ECC Control Register, 6.2.9 NVM ECC Status Register, 6.2.10 NVM ECC Fault Injection Pointer Register, 6.2.11 NVM ECC Fault Injection Address Register, 6.2.12 NVM ECC Error Address Register, 6.2.13 NVM ECC Error Data 0 Register, 6.2.14 NVM ECC Error Data 1 Register, 6.2.15 NVM ECC Error Data 2 Register, 6.2.16 NVM ECC Error Data 3 Register, 6.2.17 NVM ECC Value Register, 6.2.18 NVM ECC Syndrome Register, 6.2.19 NVM CRC Control Register, 6.2.20 NVM CRC Start Address Register, 6.2.21 NVM CRC End Address Register, 6.2.22 NVM CRC Seed Register, 6.2.23 NVM CRC Output Data Register, 7.1.3 FDEVOPT Configuration Register, 7.1.6 FPRxST Configuration Register, 7.1.7 FPRxEND Configuration Register, 7.1.8 FIRT Configuration Register, 7.1.10 FPED Configuration Register, 7.1.11 FEPUCB Configuration Register, 7.1.12 FWPUCB Configuration Register, 7.2.2 Device ID Register, 9.2.1 Reset Control Register, 10.4.3 Interrupt Control Register 3, 10.4.5 Interrupt Control Register 5, 10.4.6 Interrupt Control and Status Register, 10.4.7 Interrupt Vector Base Address Register, 10.4.9 Interrupt Request Flags Register 0, 10.4.10 Interrupt Request Flags Register 1, 10.4.11 Interrupt Request Flags Register 2, 10.4.13 Interrupt Request Flags Register 4, 10.4.14 Interrupt Request Flags Register 5, 10.4.15 Interrupt Request Flags Register 6, 10.4.16 Interrupt Request Flags Register 7, 10.4.18 Interrupt Enable Register 0, 10.4.19 Interrupt Enable Register 1, 10.4.20 Interrupt Enable Register 2, 10.4.22 Interrupt Enable Register 4, 10.4.23 Interrupt Enable Register 5, 10.4.24 Interrupt Enable Register 6, 10.4.25 Interrupt Enable Register 7, 10.4.26 Interrupt Enable Register 8, 10.4.27 Interrupt Priority Register 0, 10.4.28 Interrupt Priority Register 1, 10.4.29 Interrupt Priority Register 2, 10.4.30 Interrupt Priority Register 3, 10.4.33 Interrupt Priority Register 6, 10.4.35 Interrupt Priority Register 8, 10.4.37 Interrupt Priority Register 10, 10.4.38 Interrupt Priority Register 11, 10.4.39 Interrupt Priority Register 12, 10.4.43 Interrupt Priority Register 16, 10.4.45 Interrupt Priority Register 18, 10.4.47 Interrupt Priority Register 20, 11.3.24 Peripheral Pin Select Input Register 14, 12.3.13 User Clock Diagnostics Control Register, 12.3.2 Oscillator Configuration Register, 12.3.5 Clock Generator Control Register, 12.3.10 PLL Divider Register, 12.3.12 Reset Control Register, 12.3.14 Clock Monitor Control Register, 12.3.15 Clock Monitor Control Register, 12.3.16 Clock Monitor Prescaler Register, 13.3.1 DMA Module Control Register, 13.3.2 DMA Data Buffer Register, 13.3.5 DMA Channel x Control Register, 13.3.10 DMA Channel x Count Register, 14.3.2.1 PWM Clock Control Register, 14.3.3.1 PWM Generator x Control Register, 14.3.3.13 PWM Generator x Period Register, 14.3.3.16 PWM Generator x Trigger C Register, 15.3.1 ADC n Control Register, 15.3.2 ADC n Test Mode Data Register, 15.3.3 ADC n Result Ready Flags Register, 15.3.4 ADC n Comparators Status Register, 15.3.5 ADC n Software Triggers Request Register, 15.3.6 ADC 1 Channel x Control Register, 15.3.7 ADC 1 Channel x Result Register, 15.3.8 ADC 1 Channel x Counter Register, 15.3.9 ADC 1 Channel x Low Compare Register, 15.3.10 ADC 1 Channel x High Compare Register, 15.3.11 ADC 1 Channel x Secondary Accumulator Register, 16.3.1 DAC Control 1 Register, 16.3.2 DAC Control 2 Register, 17.3.3 QEI Status Register, 18.3.1 UARTx Configuration Register, 18.3.2 UARTx Status Register, 18.3.6 UARTx Timing Parameter A Register, 18.3.10 UARTx Interrupt Register, 21.3.1 SENTx Control Register 1, 21.3.4 SENTx Status Register, 21.3.6 SENTx Data Register, 22.3.1 BiSS Single Cycle Data Register, 22.3.2 BiSS Single Cycle Data Register, 22.3.3 BiSS 1 Register Data Register, 22.3.4 BiSS Client Configuration Register, 27.2.21 CRC Control Register, 26.3.1 PTG Control Register, 27.2.1 CRC Control Register, 27.2.2 CRC XOR Register, 27.2.3 CRC Data Register, 27.2.4 CRC Shift Register, 32.2.1 Reset Control Register, 32.2.3 Peripheral Module Disable 2 Register, 32.2.4 Peripheral Module Disable 3 Register and 32.2.3 Peripheral Module Disable 2 Register.
    • Added 7.1.9 FSECDBG Configuration Register, 15.3.12 ADC 2 Channel x Control Register, 15.3.13 ADC 2 Channel x Result Register, 15.3.14 ADC 2 Channel x Counter Register, 15.3.15 ADC 2 Channel x Low Compare Register, 15.3.16 ADC 2 Channel x High Compare Register and 15.3.17 ADC 2 Channel x Secondary Accumulator Register.
    • Removed NVM Address Register (Duplicate) and NVM ECC Fault Injection Address Register (Duplicate).
  • Figures
    • Updated Figure 1. 28-Pin SSOP, Figure 2. 28-Pin VQFN, Figure 3. 36-Pin VQFN, Figure 4. 48-Pin VQFN, TQFP, Figure 5. 64-Pin VQFN, TQFP, Figure 1-1. dsPIC33AK128MC106 Family Block Diagram, Figure 2-1. Recommended Minimum Connection, 2.3 Master Clear (MCLR) Pin, 2.4 ICSP Pins, Figure 3-12. Conventional and Convergent Rounding ModesFigure 3-14. Modulo Addressing Operation Example, Figure 4-1. Memory Map for dsPIC33AK128MC106, Figure 5-3. BIST Flowchart, Figure 8-2. PAC Locking Behavior, Figure 9-1. System Reset Block Diagram, Figure 12-1. Oscillator Module Block Diagram, Figure 12-2. Clock Generator, Figure 12-4. PLL Block Diagram, Figure 12-9. Clock Monitor Architecture, Figure 12-13. Frequency Measurement Function – CPU, Figure 12-5. Crystal or Ceramic Resonator Operation (XT or HS Oscillator Mode), Figure 12-8. OSCO Pin for Clock Output (in EC Mode), Figure 12-10. Monitor Function, Figure 13-6. Ping-Pong Support Connection, Figure 13-7. Ping-Pong – Transmit, Figure 13-8. Ping-Pong Transmit in Steady State, Figure 13-9. Ping-Pong – Receive, Figure 13-10. Ping-Pong Receive Operation in Steady State, Figure 14-4. PWM Generator Clocking, Figure 15-2. ADC Input Model, Figure 15-1. ADC Module Block Diagram, Figure 16-1. High-Speed Analog Comparator Module Block Diagram, Figure 17-2. Quadrature Encoder Interface (QEI) Module Block Diagram, Figure 19-1. SPIx Module Block Diagram, Figure 18-1. Simplified UARTx Block Diagram, Figure 18-8. Asynchronous Transmitter Block Diagram, Figure 18-9. Asynchronous Receiver Block Diagram, Figure 18-15. Smart Card Subsystem, Figure 22-7. Clock Tree, Figure 23-1. Timer1 Block Diagram, Figure 23-2. Timer1 Clock Input Logic, Figure 21-1. SENTx Module Block Diagram, Figure 21-3. SENTx Transmit Mode Block Diagram, Figure 21-4. SENTx Data Transmission, Asynchronous Mode, Figure 21-6. SENTx Data Transmission, Synchronous Mode, Figure 21-7. SENTx Receive Mode Block Diagram, Figure 30-1. Watchdog Timer Block Diagram, Figure 28-1. Current Bias Generator Sources, Figure 28-2. 10 μA Current Source, Figure 28-4. Single-Ended Positive Voltage Shift, Figure 32-1. Wake-up Delay from Sleep Mode, Figure 37-1. Load Conditions for Device Timing Specifications, Figure 37-2. External Clock Timing, Figure 37-7. QEI Module Index Pulse Timing Characteristics, Figure 37-11. SPIx Host Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 1) Timing Characteristics, Figure 37-12. SPIx Client Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 0) Timing Characteristics and Figure 37-13. SPIx Client Mode (Full-Duplex, CKE = 1, CKP = x, SMP = 0) Timing Characteristics, Table 37-17. I/O Pin Input Leakage Specifications, Table 37-27. Reset and Watchdog Timer Timing Requirements, Table 37-32. SPIx Host Mode (Full-Duplex, CKE = 1, CKP = X, SMP = 1), Table 37-39. ADC Module Specificationsand Table 37-42. DACx Module Specifications.
    • Added Figure 12-3. Peripheral Clock Divider Block Diagram
    • Removed REPEAT [W] Instruction Flow and Connecting DAC Output to the Op Amp Internally.
  • Examples:
    • Updated Example 3-2. File Register Instructions, Example 12-4. Code Example for Using PLL with 8 MHz Internal FRC, Example 13-1. Typical Code Sequence for a One-Shot Transfer, Example 13-2. Typical Code Sequence for a Repeated One-Shot Transfer, Example 13-3. Typical Code Sequence for a Continuous Transfer, Example 14-3. Typical Code Sequence for a Repeated Continuous Transfer, Example 13-5. Code for Fixed to Block Continuous Transfer (Peripheral to Memory), Example 14-1. Six-Step PWM Scheme 1 Code, Example 14-2. Six-Step PWM Scheme 2 Code, Example 14-3. Six-Step PWM Scheme 3 Code, Example 14-4. Three-Phase Sinusoidal PMSM/ACIM Motor Control Code, Example 14-5. Complementary PWM Output Mode, Example 14-6. Cycle-by-Cycle Current Limit Mode, Example 14-7. External Period Reset Mode, Example 18-1. UART1 Transmission with Interrupts, Example 18-2. UART1 Reception with Interrupts, Example 18-3. Address Detect Transmission, Example 18-4. Address Detect Reception, Example 21-2. SENT1 Asynchronous Transmission Code, Example 21-3. SENT1 Synchronous Transmission Code, Example 21-4. SENT1 Reception Code, Example 21-5. Short PWM Code (SPC) Support, Example 21-6. SENT Reception (SPC Pulse Transmission), Example 23-2. Synchronous External Counter Example Code and Example 23-4. 32-bit Asynchronous Counter Mode Code, Example 21-2. SENT1 Asynchronous Transmission Code, Example 21-3. SENT1 Synchronous Transmission Code, Example 21-4. SENT1 Reception Code, Example 21-5. SENT Transmission (SPC Pulse Reception) and Example 21-6. SENT Reception (SPC Pulse Transmission).
  • Equations:
    • Updated Equation 16-2. Determining the SLPxDAT Value, Equation 14-1. Leading-Edge Blanking Period, Equation 15-2. One Reference Voltage Gain Error Compensation Coefficient Calculation and Equation 15-3. Two Reference Voltages Gain Error Compensation Coefficient and Offset Error Calculation.

Minor grammatical corrections and formatting changes throughout the document.

Revision C (March 2025)

This revision incorporates the following updates:

  • Sections:
    • Updated Two High-Speed Analog-to-Digital Converters, Peripheral Features, Security Module, Safety Features, Qualification , Programming and Debug Interfaces, Targeted Applications, Pin Diagrams, 3.3.12.2.2 MCU Multiply Instructions, 3.3.12.4 Round Logic, 3.4 Prefetch Branch Unit (PBU), 3.4.1 Architectural Overview, 3.6.2 Architectural Overview, 3.6.2.2 Introduction to Floating Point, 3.6.3.2.2 Flush-To-Zero (FTZ), 3.6.8.1 Floating-Point Unit Registers, 3.6.8.3 FPU Register Set, 4. Memory Organization, 4.1.2.1 Unique Device Identifier (UDID), 4.4.5 Bus Error, 4.4.5.1 Valid Targets, 4.4.6.1 Instruction RAM Window Registers, 5.4.6 Error Correcting Code (ECC), 5.4.6.2 Performing Fault Injection, 7. Configuration Bits, 8. Security Module, 8.6 Peripheral Access Controller (PAC), 9.3.1 System Reset, 9.3.5 Watchdog Time-Out Reset, 9.3.8 Configuration Mismatch Reset (CM), 9.5.1 Special Function Register (SFR) Reset States, 9.5.2 Configuration Word Register Reset States, 10. Interrupt Controller, 10.2 Architectural Overview, 10.2.1 System Traps and Interrupts, 10.3 Interrupt Vector Table, 10.3.1 Remappable Interrupt Table, 10.3.2 Collapsed Interrupt Vector, 10.5.1 Reset Vector, 10.6.1 INTCON1 through INTCON5, 10.6.5 INTTREG, 10.7.1 CPU Priority, 10.8 Interrupt Sequence, 10.10.1 DISI Inhibition Of Interrupts, 10.10.2 Global Interrupt Disable, 10.12 Wake-Up From Sleep, Idle, 10.13.1 Interrupt Latency, 11.4.12 I/O integrity Module (IOIM),12.2 Architectural Overview, 12.2.1 Peripheral Clock Divider,12.4.1.1 Fail-Safe Clock Monitor (FSCM), 12.4.2 Phase-Locked Loop (PLL), 12.4.2.1 Input Clock Limitation at Start-up for PLL Mode, 12.4.2.3.1 Setup for Using PLL with the Primary Oscillator (POSC), 12.4.2.3.2 Setup for Using PLL with 8 MHz Internal FRC, 12.4.3 Primary Oscillator (POSC), 13. Direct Memory Access (DMA) Controller, 13.4.10.2 Null Write Mode, 13.4.10.3 DMA ECC Mode, 13.4.11 Ping-Pong, 13.4.11.1 Ping-Pong Data Transmit, 13.4.12 Bit Manipulation, 13.4.13 Channel Chaining, 13.4.14 Pattern Match, 13.4.14.1 Real-Time Pattern Matching, 13.5.2 Standard Operation (Data Transfer), 13.6.1.4 Pattern Match Interrupt, 13.6.2.2 Bus Read Error, 13.6.2.3 Bus Write Error,13.7.3 Peripheral Module Disable (PMD) Register, 14. High-Resolution Pulse-Width Modulation (PWM), 14.4.2.2 PWM Operating Modes, 14.4.2.2.1.1 Multiphase Systems in Independent Edge, 15. High-Speed, Low Latency ADC, 15.4.1 Channels, 15.4.2 Analog Inputs, 15.4.3 Sampling and Conversion Timing, 15.4.4 Conversions, 15.4.5 Triggers,15.4.7 Comparator, 15.4.8 Interrupts, 15.4.10 Result Formatting, 15.4.12 Filter (Secondary Accumulator), 16.4.1.5 Pulse Stretcher, 16.4.2 Pulse Density Modulation (PDM) DAC, 16.4.2.2 Slope Generation Mode, 17.5 Application Example, 18.4.1.2 Fractional Division Mode, 18.4.1.3 UART Baud Rate Tables, 18.4.1.4 Auto-Baud Feature, 19.4.1 Modes of Operation, 19.4.1.1 SPI Host Mode Clock Frequency, I2S Audio Host Mode of Operation, 20.5.3.2 Host Clock Synchronization, 21.4.1.1 Timing Calculations for Transmit Mode, 21.4.2.1 Receive Mode Timing Calculations, 22. Bidirectional Serial Synchronous (BiSS) Module, 22.5.1 Sensor Communication Code Example, 22.5.2 Read Register Code Example, 22.5.3 Write Register Code Example, 22.5.4 Broadcast Command Code Example,22.5.5 Addressed Command Code Example, 23. Timer1, 23.2 Architectural Overview, 23.4.3 Gated Timer Mode, 24.2 Architectural Overview, 24.4.4 Output Compare and PWM Modes, 29.4.4 Differential Input Mode, 29.4.5 Enable Output Monitor, 29.4.6 Input Offset Trim and 35. Instruction Set Summary,
    • Added 10.9.1.2 Bus Error Trap During Vector Fetch.
    • Removed FPU Hazards, FPU Structural Hazards, FPU Data Hazards, Instruction/Hazard Tracker, CPU Write Stalls, FPU Instruction Kill, Register Locking and Unlocking, , Memory Boundary, Ping Pong Transmit Steady State, Ping Pong Transmit Initialization, Ping-Pong Data Receive, Ping Pong Receive Steady State, Ping Pong Receive Initialization,38.1 Package Marking Information and Product Identification System.
  • Tables:
    • Updated Table 2. 28-Pin SSOP Complete Pin Function Descriptions, Table 4-2. UDID Address, Table 5. 48-Pin VQFN, TQFP Complete Pin Function Descriptions, Table 7. Pinout I/O Descriptions, Table 3-22. MCU Instructions that Utilize the Multiplier, Table 7-2. dsPIC33AK128MC106 Configuration Addresses, Table 7-3. dsPIC33AK128MC106 Backup Configuration Addresses, Table 10-1. Interrupt Vector Details, Table 10-59. Trap Vector Details, Table 11-11. Pin Correlation to Input Remap #, Table 12-5. Clock Monitor CNTSEL/WINSEL Input Clock Selection, Table 13-2. DMA Channel Trigger Sources, Table 13-7. RELOADS/RELOADD/RELOADC Bits and Data Transfer Modes, Table 15-1. ADC Summary, Table 15-4. TRG2SRC Trigger Source Selection Bits, Table 15-5. Output Format, Table 16-7. FPDMDAC Calibration Register, Table 18-1. UART Summary, Table 18-2. UART Clock (FUART) Source Selection bits, Table 18-8. Interrupts, Table 18-13. UART Baud Rates (CLKMOD = 0 and BRGS = 0), Table 18-14. UART Baud Rates (CLKMOD = 0 and BRGS = 1), Table 18-15. UART Baud Rates (CLKMOD = 1), Table 19-2. SPI Host Clock Source Selection bit, Table 19-3. SPI FIFO Depth, Table 19-13. Sample SCKx Frequencies, Table 20-19. I2C Clock Rates, Table 23-1. Timer Summary Table, Table 23-2. Timer Clock Source Select bit, Table 24-2. CLKSEL Time Base Clock Select bits, Table 24-20. Synchronization Sources, Table 28-4. Selectable Source Option, Table 29-1. Op Amp Summary Table, Table 35-2. Instruction Set Overview, Table 37-21. ESD and Latch-Up Specifications, Table 37-24. PLLn Timing Specifications, Table 37-39. UARTx Module I/O Timing Requirements and Table 37-43. DACx Module Specifications.
    • Added a new Register Bit Attribute Legend table to all registers.
  • Registers:
    • Updated 3.2.5 Core Mode Control Register, 3.4.2.1 Cache Control Register, 3.4.2.2 Cache Status Register, 3.6.4 Floating-Point Data Register (F0-F31), 3.6.5 Floating-Point Control Register, 3.6.6 Floating-Point Status Register, 3.6.7 Floating-Point Exception Address Capture Register, 4.3.4 BMX Error Status Register for X Data Bus, 4.3.5 BMX Error Status Register for Y Data Bus, 4.3.6 BMX Error Status Register for DMA, 4.3.8 BMX Error Status Register for NVM, 4.3.9 BMX Error Status Register for ICD, 5.3.1 RAM ECC Control Register, 5.3.2 RAM ECC Status Register, 5.3.3 RAM ECC Fault Pointer Register, 5.3.4 RAM ECC Fault Injection Address Register, 5.3.5 RAM ECC Error Address Register, 5.3.6 RAM ECC Error Data Register, 5.3.7 RAM ECC Value Register, , 5.3.8 RAM ECC Syndrome Register,5.3.9 PWB ECC RAM Control Register, 5.3.10 PWB ECC RAM Status Register,5.3.11 PWB ECC RAM Fault Pointer Register, 5.3.12 PWB ECC RAM Fault Injection Address Register, 5.3.13 PWB ECC RAM Error Address Register, 5.3.14 PWB ECC RAM Error Data Register, 5.3.15 PWB ECC RAM Value Register, 5.3.16 PWB ECC Syndrome Register, 6.2.20 NVM CRC Start Address Register, 6.2.21 NVM CRC End Address Register, 7.1.3 FDEVOPT Configuration Register, 7.1.11 FEPUCB Configuration Register, 8.2.2 IRT Control Register, 9.2.1 Reset Control Register, 10.4.10 Interrupt Request Flags Register 1, 10.4.19 Interrupt Enable Register 1, 10.4.45 Interrupt Priority Register 18 through 10.4.57 Interrupt Priority Register 34, 11.3.29 Peripheral Pin Select Input Register 19, 11.3.30 Peripheral Pin Select Input Register 20, 11.3.31 Peripheral Pin Select Input Register 21, 12.3.2 Oscillator Configuration Register, 13.3.5 DMA Channel x Control Register, 13.3.6 DMA Channel x Selection Register, 13.3.7 DMA Channel x Status Register, 13.3.8 DMA Channel x Source Address Register, 13.3.9 DMA Channel x Destination Address Register, 13.3.10 DMA Channel x Count Register, 13.3.11 DMA Channel x Clear Register, 13.3.12 DMA Channel x Set Register, 13.3.13 DMA Channel x Invert Register, 13.3.14 DMA Channel x Mask Register, 15.3.1 ADC n Control Register, 15.3.2 ADC n Test Mode Register, 15.3.3 ADC n Result Ready Status Flags Register, 15.3.5 ADC n Software Trigger Request Register, 15.3.6 ADC 1 Channel x Control Register, 15.3.7 ADC 1 Channel x Data Result Register, 15.3.9 ADC 1 Channel x Compare Low Register, 15.3.10 ADC 1 Channel x Compare High Register, 15.3.12 ADC 2 Channel x Control Register, 15.3.13 ADC 2 Channel x Data Result Register, 15.3.15 ADC 2 Channel x Compare Low Register, 15.3.16 ADC 2 Channel x Compare High Register, 16.3.5 DAC Slope x Control Register, 17.3.1 QEI Control Register, 18.3.2 UARTx Status Register, 18.3.6 UARTx Timing Parameter A Register, 18.3.7 UARTx Timing Parameter B Register, 19.3.1 SPIx Control Register 1, 19.3.4 SPI Buffer Register, 19.3.5 SPIx Baud Rate Generator Register, 21.3.1 SENTx Control Register 1, 21.3.2 SENTx Control Register 2, 21.3.3 SENTx Control Register 322.3.3 BiSS 1 Register Data Register, 22.3.6 BiSS Control Communication Configuration Register, 22.3.9 BiSS Communication Status Register, 22.3.10 BiSS Instruction Register, 23.3.1 Timer1 Control Register and 29.3.1 AMPx Control Register 1 .
    • Removed Peripheral Pin Select Input Register 4 (RPINR4), Peripheral Pin Select Output Register 3 (RPOR3), Peripheral Pin Select Output Register 7 (RPOR7), Peripheral Pin Select Output Register 11 (RPOR11)
  • Figures
    • Updated Figure 1-1. dsPIC33AK128MC106 Family Block Diagram, Figure 2-1. Recommended Minimum Connection, Figure 3-1. dsPIC33A Core Conceptual Block Diagram with FPU Coprocessor, Figure 3-9. DSP Engine Block Diagram, Figure 3-10. Integer and Fractional Representation of 0x40000001, Figure 3-11. Integer and Fractional Representation of 0xC0000002, Figure 8-2. PAC Locking Behavior, Figure 13-2. DMA Channel Controllers Block Diagram, Figure 13-3. Types of DMA Data Transfers, Figure 13-4. Common Logic Flow for Data Transfer Modes, Figure 13-5. Null Write Mode, Figure 13-6. Ping-Pong Support Connection, Figure 13-7. Ping-Pong – Transmit, Figure 15-1. ADC Module Block Diagram, Figure 18-3. UART Clocking Diagram, Figure 18-4. Fractional Division Mode, Figure 19-8. SPIx Host/Client Connection Diagram, Figure 19-12. SPIx Host, Frame Host Connection Diagram, Figure 23-1. Timer1 Block Diagram, Figure 29-1. Basic Op Amp Block Diagram and Figure 30-1. Watchdog Timer Block Diagram.
    • Removed Timer1 Clock Input Logic
  • Examples:
    • Updated Example 10-3. ISR for Timer 1 Interrupt, Example 12-1, Example 12-3. Code Example for Using PLL with the Primary Oscillator (POSC), Example 12-4. Code Example for Using PLL with 8 MHz Internal FRC, Example 13-3. Typical Code Sequence for a Continuous Transfer, Example 13-4. Typical Code Sequence for a Repeated Continuous Transfer, Example 13-5. Code for Fixed to Block Continuous Transfer (Peripheral to Memory), Example 13-6. Null-Write Mode, Example 15-3. Gain Error Calibration Example, Example 15-4. Single Conversion Example, Example 15-5. Windowed Conversions Example, Example 15-6. Integration of the Multiple Samples Example, Example 15-7. Oversampling Example,Example 15-8. Comparator Example, Example 15-9. Multiple Channels Scan Example, Example 15-10. Second Order Low Pass Filter Example,Example 16-4. Initialize DAC with Slope Compensation, Example 16-5. DAC Settings for Hysteretic Mode, Example 18-1. UART1 Transmission with Interrupts, Example 18-2. UART1 Reception with Interrupts, Example 18-3. Address Detect Transmission, Example 18-4. Address Detect Reception, Example 19-1. Initialization Code for 16-Bit SPI Host Mode, Example 21-2. SENT1 Asynchronous Transmission Code, Example 21-3. SENT1 Synchronous Transmission Code, Example 21-4. SENT1 Reception Code, Example 21-5. SENT Transmission (SPC Pulse Reception), Example 21-6. SENT Reception (SPC Pulse Transmission), Example 24-1. Setup for Input Capture mode (Every Rising Edge)Example 26-6. Interleaved Sampling Step Command Program, Example 26-7. Ratioed Sampling Step Command Program, Example 28-2. Single-Ended Positive Voltage Shift with 50 μA Selection and Example 30-3. WDT Configuration Example.
    • Added Example 5-1. Program Execution from RAM,
  • Equations:
    • Updated Equation 18-1. Baud Rate When BRG = 0, Equation 18-3. Baud Rate Formulas, Equation 19-1. SCKx Frequency, Equation 19-2. Baud Rate Calculation, Equation 20-1. BRG Reload Value Calculation and Equation 21-1. Tick Period Calculation,
    • Added Equation 12-1. FRACDIV,
Minor grammatical corrections and formatting changes throughout the document.