16.6.9 APBC Mask

Name: APBCMASK
Offset: 0x1C
Reset: 0x00002000
Property: PAC Write-Protection

Bit 3130292827262524 
          
Access  
Reset  
Bit 2322212019181716 
          
Access  
Reset  
Bit 15141312111098 
  CCLQSPI ICMTRNGAESAC 
Access R/WR/WR/WR/WR/WR/W 
Reset 010000 
Bit 76543210 
 PDECTC5TC4TCC3TCC2GMAC   
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 

Bit 14 – CCL CCL APBC Mask Clock Enable

ValueDescription
0 The APBC clock for the CCL is stopped.
1 The APBC clock for the CCL is enabled.

Bit 13 – QSPI QSPI APBC Mask Clock Enable

ValueDescription
0 The APBC clock for the QSPI is stopped.
1 The APBC clock for the QSPI is enabled.

Bit 11 – ICM ICM APBC Mask Clock Enable

ValueDescription
0 The APBC clock for the ICM is stopped.
1 The APBC clock for the ICM is enabled.

Bit 10 – TRNG TRNG APBC Mask Clock Enable

ValueDescription
0 The APBC clock for the TRNG is stopped.
1 The APBC clock for the TRNG is enabled.

Bit 9 – AES AES APBC Mask Clock Enable

ValueDescription
0 The APBC clock for the AES is stopped.
1 The APBC clock for the AES is enabled.

Bit 8 – AC AC APBC Mask Clock Enable

ValueDescription
0 The APBC clock for the AC is stopped.
1 The APBC clock for the AC is enabled.

Bit 7 – PDEC PDEC APBC Mask Clock Enable

ValueDescription
0 The APBC clock for the PDEC is stopped.
1 The APBC clock for the PDEC is enabled.

Bits 5, 6 – TCn TCn APBC Mask Clock Enable

ValueDescription
0 The APBC clock for the TCn is stopped.
1 The APBC clock for the TCn is enabled.

Bits 3, 4 – TCCn TCCn APBC Mask Clock Enable

ValueDescription
0 The APBC clock for the TCCn is stopped.
1 The APBC clock for the TCCn is enabled.

Bit 2 – GMAC GMAC APBC Mask Clock Enable

ValueDescription
0 The APBC clock for the GMAC is stopped.
1 The APBC clock for the GMAC is enabled.