37.8.8 Rx Serializer Control
| Name: | RXCTRL |
| Offset: | 0x24 |
| Reset: | 0x00000000 |
| Property: | Enable-Protected, PAC Write-Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| RXLOOP | DMA | MONO | |||||||
| Access | R/W | R/W | R/W | ||||||
| Reset | 0 | 0 | 0 |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| SLOTDIS7 | SLOTDIS6 | SLOTDIS5 | SLOTDIS4 | SLOTDIS3 | SLOTDIS2 | SLOTDIS1 | SLOTDIS0 | ||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| BITREV | EXTEND[1:0] | WORDADJ | DATASIZE[2:0] | ||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| SLOTADJ | CLKSEL | SERMODE[1:0] | |||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
Bit 26 – RXLOOP Loop-back Test Mode
This bit enables a loop-back test mode:
| Value | Description |
|---|---|
| 0 | Each Receiver uses its SDn pin as input (default mode). |
| 1 | Receiver uses as input the transmitter output of the other Serializer in the pair: e.g. SD1 for SD0 or SD0 for SD1. |
Bit 25 – DMA Single or Multiple DMA Channels
This bit selects whether even- and odd-numbered slots use separate DMA channels or the same DMA channel.
| DMA | Name | Description |
|---|---|---|
| 0x0 | SINGLE | Single DMA channel |
| 0x1 | MULTIPLE | One DMA channel per data channel |
Bit 24 – MONO Mono Mode.
| MONO | Name | Description |
|---|---|---|
| 0x0 | STEREO | Normal mode |
| 0x1 | MONO | Left channel data is duplicated to right channel |
Bits 16, 17, 18, 19, 20, 21, 22, 23 – SLOTDISx Slot x Disabled for this Serializer [x=7..0]
This field allows disabling some slots in each transmit frame:
| Value | Description |
|---|---|
| 0 | Slot x is used for data transfer. |
| 1 | Slot x is not used for data transfer and will be output as specified in the TXDEFAULT field. |
Bit 15 – BITREV Data Formatting Bit Reverse
This bit allows changing the order of data bits in the word in the Formatting Unit.
| BITREV | Name | Description |
|---|---|---|
| 0x0 | MSBIT | Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) |
| 0x1 | LSBIT | Transfer Data Least Significant Bit (LSB) first |
Bits 14:13 – EXTEND[1:0] Data Formatting Bit Extension
This field defines the bit value used to extend data samples in the Formatting Unit.
| EXTEND[1:0] | Name | Description |
|---|---|---|
| 0x0 | ZERO | Extend with zeros |
| 0x1 | ONE | Extend with ones |
| 0x2 | MSBIT | Extend with Most Significant Bit |
| 0x3 | LSBIT | Extend with Least Significant Bit |
Bit 12 – WORDADJ Data Word Formatting Adjust
This field defines left or right adjustment of data samples in the word in the Formatting Unit. for details.
| WORDADJ | Name | Description |
|---|---|---|
| 0x0 | RIGHT | Data is right adjusted in word |
| 0x1 | LEFT | Data is left adjusted in word |
Bits 10:8 – DATASIZE[2:0] Data Word Size
This field defines the number of bits in each data sample. For 8-bit compact stereo, two 8-bit data samples are packed in bits 15 to 0 of the DATAm register. For 16-bit compact stereo, two 16-bit data samples are packed in bits 31 to 0 of the DATAm register.
| DATASIZE[2:0] | Name | Description |
|---|---|---|
| 0x0 | 32 | 32 bits |
| 0x1 | 24 | 24 bits |
| 0x2 | 20 | 20 bits |
| 0x3 | 18 | 18 bits |
| 0x4 | 16 | 16 bits |
| 0x5 | 16C | 16 bits compact stereo |
| 0x6 | 8 | 8 bits |
| 0x7 | 8C | 8 bits compact stereo |
Bit 7 – SLOTADJ Data Slot Formatting Adjust
This field defines left or right adjustment of data samples in the slot.
| SLOTADJ | Name | Description |
|---|---|---|
| 0x0 | RIGHT | Data is right adjusted in slot |
| 0x1 | LEFT | Data is left adjusted in slot |
Bit 5 – CLKSEL Clock Unit Selection.
| CLKSEL | Name | Description |
|---|---|---|
| 0x0 | CLK0 | Use Clock Unit 0 |
| 0x1 | CLK1 | Use Clock Unit 1 |
Bits 1:0 – SERMODE[1:0] Serializer Mode.
| SERMODE[1:0] | Name | Description |
|---|---|---|
| 0x0 | RX | Receive |
| 0x1 | Reserved | |
| 0x2 | PDM2 | Receive one PDM data on each serial clock edge |
| 0x3 | Reserved |