40.9.6 Device EndPoint Interrupt Enable n

This register allows the user to enable an interrupt without doing a read-modify-write operation. Changes in this register will also be reflected in the Endpoint Interrupt Enable Set (EPINTENSET) register.
Name: EPINTENCLRn
Offset: 0x0108 + n*0x20 [n=0..7]
Reset: 0x00
Property: PAC Write-Protection

Bit 76543210 
  STALL1STALL0RXSTPTRFAIL1TRFAIL0TRCPT1TRCPT0 
Access R/WR/WR/WR/WR/WR/WR/W 
Reset 0200202 

Bits 5, 6 – STALL Transmit STALL x Interrupt Enable

Writing a zero to this bit has no effect.

Writing a one to this bit will clear the Transmit Stall x Interrupt Enable bit and disable the corresponding interrupt request.

ValueDescription
0 The Transmit Stall x interrupt is disabled.
1 The Transmit Stall x interrupt is enabled and an interrupt request will be generated when the Transmit Stall x Interrupt Flag is set.

Bit 4 – RXSTP Received Setup Interrupt Enable

Writing a zero to this bit has no effect.

Writing a one to this bit will clear the Received Setup Interrupt Enable bit and disable the corresponding interrupt request.

ValueDescription
0 The Received Setup interrupt is disabled.
1 The Received Setup interrupt is enabled and an interrupt request will be generated when the Received Setup Interrupt Flag is set.

Bits 2, 3 – TRFAIL Transfer Fail x Interrupt Enable

The user should look into the descriptor table status located in ram to be informed about the error condition : ERRORFLOW, CRC.

Writing a zero to this bit has no effect.

Writing a one to this bit will clear the Transfer Fail x Interrupt Enable bit and disable the corresponding interrupt request.

ValueDescription
0 The Transfer Fail bank x interrupt is disabled.
1 The Transfer Fail bank x interrupt is enabled and an interrupt request will be generated when the Transfer Fail x Interrupt Flag is set.

Bits 0, 1 – TRCPT Transfer Complete x interrupt Enable

Writing a zero to this bit has no effect.

Writing a one to this bit will clear the Transfer Complete x interrupt Enable bit and disable the corresponding interrupt request.

ValueDescription
0 The Transfer Complete bank x interrupt is disabled.
1 The Transfer Complete bank x interrupt is enabled and an interrupt request will be generated when the Transfer Complete x Interrupt Flag is set.