40.9 Device Endpoint n Register Summary
| Offset | Name | Bit Pos. | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|
0x00 ... 0xFF | Reserved | |||||||||
| 0x0100 | EPCFG0 | 7:0 | EPTYPE1[2:0] | EPTYPE0[2:0] | ||||||
0x0101 ... 0x0103 | Reserved | |||||||||
| 0x0104 | EPSTATUSCLR0 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| 0x0105 | EPSTATUSSET0 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| 0x0106 | EPSTATUS0 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| 0x0107 | EPINTFLAG0 | 7:0 | STALL1 | STALL0 | RXSTP | TRFAIL1 | TRFAIL0 | TRCPT1 | TRCPT0 | |
| 0x0108 | EPINTENCLR0 | 7:0 | STALL1 | STALL0 | RXSTP | TRFAIL1 | TRFAIL0 | TRCPT1 | TRCPT0 | |
| 0x0109 | EPINTENSET0 | 7:0 | STALL1 | STALL0 | RXSTP | TRFAIL1 | TRFAIL0 | TRCPT1 | TRCPT0 | |
0x010A ... 0x011F | Reserved | |||||||||
| 0x0120 | EPCFG1 | 7:0 | EPTYPE1[2:0] | EPTYPE0[2:0] | ||||||
0x0121 ... 0x0123 | Reserved | |||||||||
| 0x0124 | EPSTATUSCLR1 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| 0x0125 | EPSTATUSSET1 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| 0x0126 | EPSTATUS1 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| 0x0127 | EPINTFLAG1 | 7:0 | STALL1 | STALL0 | RXSTP | TRFAIL1 | TRFAIL0 | TRCPT1 | TRCPT0 | |
| 0x0128 | EPINTENCLR1 | 7:0 | STALL1 | STALL0 | RXSTP | TRFAIL1 | TRFAIL0 | TRCPT1 | TRCPT0 | |
| 0x0129 | EPINTENSET1 | 7:0 | STALL1 | STALL0 | RXSTP | TRFAIL1 | TRFAIL0 | TRCPT1 | TRCPT0 | |
0x012A ... 0x013F | Reserved | |||||||||
| 0x0140 | EPCFG2 | 7:0 | EPTYPE1[2:0] | EPTYPE0[2:0] | ||||||
0x0141 ... 0x0143 | Reserved | |||||||||
| 0x0144 | EPSTATUSCLR2 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| 0x0145 | EPSTATUSSET2 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| 0x0146 | EPSTATUS2 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| 0x0147 | EPINTFLAG2 | 7:0 | STALL1 | STALL0 | RXSTP | TRFAIL1 | TRFAIL0 | TRCPT1 | TRCPT0 | |
| 0x0148 | EPINTENCLR2 | 7:0 | STALL1 | STALL0 | RXSTP | TRFAIL1 | TRFAIL0 | TRCPT1 | TRCPT0 | |
| 0x0149 | EPINTENSET2 | 7:0 | STALL1 | STALL0 | RXSTP | TRFAIL1 | TRFAIL0 | TRCPT1 | TRCPT0 | |
0x014A ... 0x015F | Reserved | |||||||||
| 0x0160 | EPCFG3 | 7:0 | EPTYPE1[2:0] | EPTYPE0[2:0] | ||||||
0x0161 ... 0x0163 | Reserved | |||||||||
| 0x0164 | EPSTATUSCLR3 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| 0x0165 | EPSTATUSSET3 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| 0x0166 | EPSTATUS3 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| 0x0167 | EPINTFLAG3 | 7:0 | STALL1 | STALL0 | RXSTP | TRFAIL1 | TRFAIL0 | TRCPT1 | TRCPT0 | |
| 0x0168 | EPINTENCLR3 | 7:0 | STALL1 | STALL0 | RXSTP | TRFAIL1 | TRFAIL0 | TRCPT1 | TRCPT0 | |
| 0x0169 | EPINTENSET3 | 7:0 | STALL1 | STALL0 | RXSTP | TRFAIL1 | TRFAIL0 | TRCPT1 | TRCPT0 | |
0x016A ... 0x017F | Reserved | |||||||||
| 0x0180 | EPCFG4 | 7:0 | EPTYPE1[2:0] | EPTYPE0[2:0] | ||||||
0x0181 ... 0x0183 | Reserved | |||||||||
| 0x0184 | EPSTATUSCLR4 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| 0x0185 | EPSTATUSSET4 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| 0x0186 | EPSTATUS4 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| 0x0187 | EPINTFLAG4 | 7:0 | STALL1 | STALL0 | RXSTP | TRFAIL1 | TRFAIL0 | TRCPT1 | TRCPT0 | |
| 0x0188 | EPINTENCLR4 | 7:0 | STALL1 | STALL0 | RXSTP | TRFAIL1 | TRFAIL0 | TRCPT1 | TRCPT0 | |
| 0x0189 | EPINTENSET4 | 7:0 | STALL1 | STALL0 | RXSTP | TRFAIL1 | TRFAIL0 | TRCPT1 | TRCPT0 | |
0x018A ... 0x019F | Reserved | |||||||||
| 0x01A0 | EPCFG5 | 7:0 | EPTYPE1[2:0] | EPTYPE0[2:0] | ||||||
0x01A1 ... 0x01A3 | Reserved | |||||||||
| 0x01A4 | EPSTATUSCLR5 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| 0x01A5 | EPSTATUSSET5 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| 0x01A6 | EPSTATUS5 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| 0x01A7 | EPINTFLAG5 | 7:0 | STALL1 | STALL0 | RXSTP | TRFAIL1 | TRFAIL0 | TRCPT1 | TRCPT0 | |
| 0x01A8 | EPINTENCLR5 | 7:0 | STALL1 | STALL0 | RXSTP | TRFAIL1 | TRFAIL0 | TRCPT1 | TRCPT0 | |
| 0x01A9 | EPINTENSET5 | 7:0 | STALL1 | STALL0 | RXSTP | TRFAIL1 | TRFAIL0 | TRCPT1 | TRCPT0 | |
0x01AA ... 0x01BF | Reserved | |||||||||
| 0x01C0 | EPCFG6 | 7:0 | EPTYPE1[2:0] | EPTYPE0[2:0] | ||||||
0x01C1 ... 0x01C3 | Reserved | |||||||||
| 0x01C4 | EPSTATUSCLR6 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| 0x01C5 | EPSTATUSSET6 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| 0x01C6 | EPSTATUS6 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| 0x01C7 | EPINTFLAG6 | 7:0 | STALL1 | STALL0 | RXSTP | TRFAIL1 | TRFAIL0 | TRCPT1 | TRCPT0 | |
| 0x01C8 | EPINTENCLR6 | 7:0 | STALL1 | STALL0 | RXSTP | TRFAIL1 | TRFAIL0 | TRCPT1 | TRCPT0 | |
| 0x01C9 | EPINTENSET6 | 7:0 | STALL1 | STALL0 | RXSTP | TRFAIL1 | TRFAIL0 | TRCPT1 | TRCPT0 | |
0x01CA ... 0x01DF | Reserved | |||||||||
| 0x01E0 | EPCFG7 | 7:0 | EPTYPE1[2:0] | EPTYPE0[2:0] | ||||||
0x01E1 ... 0x01E3 | Reserved | |||||||||
| 0x01E4 | EPSTATUSCLR7 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| 0x01E5 | EPSTATUSSET7 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| 0x01E6 | EPSTATUS7 | 7:0 | BK1RDY | BK0RDY | STALLRQ1 | STALLRQ0 | CURBK | DTGLIN | DTGLOUT | |
| 0x01E7 | EPINTFLAG7 | 7:0 | STALL1 | STALL0 | RXSTP | TRFAIL1 | TRFAIL0 | TRCPT1 | TRCPT0 | |
| 0x01E8 | EPINTENCLR7 | 7:0 | STALL1 | STALL0 | RXSTP | TRFAIL1 | TRFAIL0 | TRCPT1 | TRCPT0 | |
| 0x01E9 | EPINTENSET7 | 7:0 | STALL1 | STALL0 | RXSTP | TRFAIL1 | TRFAIL0 | TRCPT1 | TRCPT0 | |