40.8.6 Device Interrupt Enable Set
| Name: | INTENSET |
| Offset: | 0x18 |
| Reset: | 0x0000 |
| Property: | PAC Write-Protection |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| LPMSUSP | LPMNYET | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| RAMACER | UPRSM | EORSM | WAKEUP | EORST | SOF | SUSPEND | |||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit 9 – LPMSUSP Link Power Management Suspend Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Link Power Management Suspend Enable bit and enable the corresponding interrupt request.
| Value | Description |
|---|---|
| 0 | The Link Power Management Suspend interrupt is disabled. |
| 1 | The Link Power Management Suspend interrupt is enabled. |
Bit 8 – LPMNYET Link Power Management Not Yet Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Link Power Management Not Yet interrupt bit and enable the corresponding interrupt request.
| Value | Description |
|---|---|
| 0 | The Link Power Management Not Yet interrupt is disabled. |
| 1 | The Link Power Management Not Yet interrupt is enabled. |
Bit 7 – RAMACER RAM Access Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the RAM Access Enable bit and enable the corresponding interrupt request.
| Value | Description |
|---|---|
| 0 | The RAM Access interrupt is disabled. |
| 1 | The RAM Access interrupt is enabled. |
Bit 6 – UPRSM Upstream Resume Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Upstream Resume Enable bit and enable the corresponding interrupt request.
| Value | Description |
|---|---|
| 0 | The Upstream Resume interrupt is disabled. |
| 1 | The Upstream Resume interrupt is enabled. |
Bit 5 – EORSM End Of Resume Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the End Of Resume interrupt Enable bit and enable the corresponding interrupt request.
| Value | Description |
|---|---|
| 0 | The End Of Resume interrupt is disabled. |
| 1 | The End Of Resume interrupt is enabled. |
Bit 4 – WAKEUP Wake-Up Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Wake Up interrupt Enable bit and enable the corresponding interrupt request.
| Value | Description |
|---|---|
| 0 | The Wake Up interrupt is disabled. |
| 1 | The Wake Up interrupt is enabled. |
Bit 3 – EORST End of Reset Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the End of Reset interrupt Enable bit and enable the corresponding interrupt request.
| Value | Description |
|---|---|
| 0 | The End of Reset interrupt is disabled. |
| 1 | The End of Reset interrupt is enabled. |
Bit 2 – SOF Start-of-Frame Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Start-of-Frame interrupt Enable bit and enable the corresponding interrupt request.
| Value | Description |
|---|---|
| 0 | The Start-of-Frame interrupt is disabled. |
| 1 | The Start-of-Frame interrupt is enabled. |
Bit 0 – SUSPEND Suspend Interrupt Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will set the Suspend interrupt Enable bit and enable the corresponding interrupt request.
| Value | Description |
|---|---|
| 0 | The Suspend interrupt is disabled. |
| 1 | The Suspend interrupt is enabled. |