3.2 Reset Structure

CoaXPress Device: The Init Monitor initiates the init_done signal, and the FPGA_POR_N signal triggers the core resets. These include the resets for the 120 MHz domain, the XCVR TX, the 50 MHz domain, and the CoaXPress IP core. The core reset, based on the 120 MHz clock, is used to drive the IMX334 camera module. The XCVR TX core reset is derived from the XCVR clock, while the 50 MHz core reset is generated using the 50 MHz clock and a CCC module PLL lock signal. These core resets from the 50 MHz domain, the XCVR TX clock, and the IMX334 module reset work together to drive the CoaXPress IP. Additionally, the 50 MHz core reset also drives the DRI and the Processor Subsystem.

The following figure shows the reset structure of the CoaXPress device.

CoaXPress Host: The 200 MHz core reset is generated based on the PLL lock of the DDR, init_done, and FPGA_POR_N. A reset signal is generated synchronously with the 200 MHz clock. Similarly, the 148.5 MHz core reset is derived from the PLL lock of the CCC, init_done, and FPGA_POR_N, and is synchronized with the 148.5 MHz clock. The 50 MHz core reset is also generated based on the PLL lock of the CCC, init_done, and FPGA_POR_N, and is synchronized with the 50 MHz clock. The 200 MHz core reset signal drives the DDR Write, DDR Arbiter, and DDR Read modules. The 148.5 MHz core reset signal is used to drive both the DDR Read and CoaXPress IP modules. The 50 MHz core reset signal drives the CoaXPress IP, PF DDR, UART IP, and the Processor Subsystem.

The following figure shows the reset structure of the CoaXPress host.