4.10.3 AVR Reset

During AVR reset, all I/O registers are set to their initial (hardware-defined) values and the AVR program starts execution from the reset vector. The following circuit diagram shows the reset logic of the ATA8210/15.

Three sources can generate an AVR reset:

DVCC-related Power-on Reset (POR) – The AVR reset is generated when the supply voltage DVCC is below the brown-out reset threshold (V_BOT-). The brown-out detector is always enabled.
External Reset (EXTR) – The AVR reset is generated when a low level is detected on the NRESET pin for longer than 10 µs.
Watchdog Reset (WDR) – The AVR reset is generated when the watchdog is enabled and its timer period expires.

Note: The RF front-end and XTO have a separate reset circuit monitoring the AVCC voltage. See Voltage Monitor (Low Battery Indicator) from Related Links.

Figure 4-83. Reset Logic of the ATA8210/15