4.10.3.1 Power On (PWRON) and Brown-out Reset (BOR)
The DVCC supply voltage regulator output is monitored permanently by the Brown-out Detector (BOD). This monitor circuit is also used during the power-up sequence. After a PWRON or NPWRONx edge event, the DVCC voltage ramps up. When reaching the VBOT+ voltage (DVCC reset level, typically 1.27V), the internal reset switches to ‘1’ and an internal timer is started. For more details on the time depends on the reset source, see Delay Time tTOUT Until Internal Reset is Removed in the AVR Reset Timing from Related Links. After the time period of tTOUT, the negative edge of the internal reset starts the AVR operation. For the complete power-up timing, see Power-Up Sequence in the AVR Reset Timing from the Related Links.
The duration of the internal reset delay, tTOUT, can be extended by an external signal applied to the NRESET pin. The DVCC voltage must already be stable. If the signal at NRESET reaches the voltage level VRST (approximately VS/2), the reset timer, tTOUT, is re-triggered to cause the internal reset.
A reset is generated when DVCC voltage drops below the internal threshold level (VBOT- , typically 1.25V). If the DVCC voltage increases again (VBOT+, typically 1.27V, 20 mV hysteresis) after the time period of tTOUT, the AVR system resumes operation. For the timing details, see AVR Reset Timing from Related Links. A typical DVCC voltage drop scenario displays in the following figure.