4.10.3.2 Watchdog Reset (WDTRESET)
When the watchdog time-out occurs, a short reset pulse of one clock cycle duration is generated. The delay timer starts counting the time-out period, tTOUT, on the falling edge of this pulse. See AVR Reset Timing from Related Links. For more details on the hardware description, see Timer0 – Watchdog/Interval Timer from Related Links.
