4.4.2.3 ADC

The sigma delta ADC converts the IF signals into the digital signal domain by using a clock coming from the fractional-N PLL.

The ADC time constants are calibrated using the RF front-end registers FEBT.RTN2[1:0] and FEBT.CTN2[1:0]. These parameters come from the factory-locked EEPROM and compensate for the process tolerances of the ADC. The values must be written to the registers before powering up the receive path.

Depending on the RF applied, different sampling rates are used within the ADC, and the RF front-end register FECR.ADHS can be enabled for higher sampling rates. The register must be set before activating the receive path. The configuration tool must be used to calculate the necessary EEPROM settings.