36.6 SPI Interrupts

There are three top level SPI interrupts in the PIRx register:

  • SPI Transmit (SPIxTXIF)
  • SPI Receive (SPIxRXIF)
  • SPI Module status (SPIxIF)

The SPI Module status interrupts are enabled at the module level in the SPIxINTE register. Only enabled status interrupts will cause the single top level SPIxIF flag to be set.