This family of devices contains a PIC18 8-bit CPU core based on the modified Harvard architecture. The PIC18 CPU supports:

  • System arbitration which decides memory access allocation depending on user priorities
  • Vectored interrupt capability with automatic two-level deep context saving
  • 127-level deep hardware stack with overflow and underflow Reset capabilities
  • Support Direct, Indirect, and Relative Addressing modes
  • 8x8 hardware multiplier
Figure 7-1. Family Block Diagram