7.1 System Arbitration

The system arbiter resolves memory access between the system level selections (i.e., Main, Interrupt Service Routine) and peripheral selection (e.g., DMA and Scanner) based on user-assigned priorities. A block diagram of the system arbiter can be found below. Each of the system level and peripheral selections has its own priority selection registers. Memory access priority is resolved using the number written to the corresponding Priority registers, '0' being the highest priority selection and the maximum value being the lowest priority. All system level and peripheral level selections default to the lowest priority configuration. If the same value is in two or more Priority registers, priority is given to the higher-listed selection according to the following table.

Important: When the PRLOCKED bit is set, the Non Volatile Memory (NVM) module has a fixed priority of '0' that cannot be changed. If an interrupt is desired when an NVM read/write operation is in progress, then the ISR priority level must be set to '0'. The NVM module priority is ignored when PRLOCKED bit is cleared.
Table 7-1. Default Priorities
Selection Priority Register Reset Value
System Level ISR 7
Peripheral DMA1 7
DMA2 7
DMA3 7
DMA4 7
DMA5 7
DMA6 7
Figure 7-2. System Arbiter Block Diagram