14.12 Power Control (PCON0/PCON1) Registers

The Power Control (PCON0/PCON1) registers contain flag bits to differentiate between the following Reset events:

  • Brown-out Reset (BOR)
  • Power-on Reset (POR)
  • Reset Instruction Reset (RI)
  • MCLR Reset (RMCLR)
  • Watchdog Timer Reset (RWDT)
  • Watchdog Window Violation (WDTWV)
  • Stack Underflow Reset (STKUNF)
  • Stack Overflow Reset (STKOVF)
  • Configuration Memory Reset (RCM)
  • Memory Violation Reset (MEMV)
  • Main LDO Voltage Regulator Reset (RVREG)

Hardware will change the corresponding register bit or bits as a result of the Reset event. Bits for other Reset events remain unchanged. See Determining the Cause of a Reset for more details.

Software will reset the bit to the Inactive state after restart (hardware will not reset the bit).

Software may also set any PCON0 bit to the Active state, so that user code may be tested, but no Reset action will be generated.